Design Verification Engineer

Role Summary

The Design Verification Engineer will be responsible for overseeing the complete verification flow, with hands-on experience in developing testbenches, Universal Verification Components (UVC), and executing test plans.

Experience Level

A minimum of 4 years of hands-on experience in ASIC design verification is preferred, demonstrating a robust understanding of functional verification and related processes.

Responsibilities

• Develop, maintain, and enhance the test environment and testbench.
• Perform IP/block testing and debugging.
• Conduct functional & code coverage analysis, as well as performance/power testing.
• Support SoC integration while bridging the gap between IP and SoC.

Requirements

Strong technical expertise is required in functional verification, test planning, and BTC development. Familiarity with Verilog, System Verilog, object-oriented programming skills, and UVM/OVM are essential. Also, debugging skills and knowledge of verification tools and methodologies are crucial.

Education Requirements

A Bachelor’s degree in Electronics and Communication (ECE), Electrical Engineering, or a Master’s degree with an emphasis in Electrical/Electronics Engineering is preferred, with a focus on VLSI major if applicable.