Design Verification Engineer

Role Summary

AMD is seeking a Design Verification Engineer for their team in Vancouver, British Columbia. This role involves engaging with complex design verification tasks aimed at AMD’s next-generation products, including the utilization of the latest UVM standards. The position requires a detail-oriented approach to ensure thorough coverage closure through effective test plan development.

Experience Level

The successful candidate should possess a strong technical foundation with experience in ASIC design verification. Ideal candidates are not only creative problem solvers but also enthusiastic about contributing to both team and individual goals in a fast-paced work environment.

Key Responsibilities

• Writing, implementing, and reviewing comprehensive test plans.
• Developing testbenches and verification components including UVCs, BFMs, and reusable verification environments.
• Maintaining and modifying random and directed test cases and libraries using System Verilog/UVM.
• Analyzing functional, code, and test plan coverage to ensure thorough testing.
• Implementing assertions, checkers, and monitors during the verification process.
• Utilizing various CAD and EDA tools for effective design verification.
• Employing industry-leading verification methodologies.
• Troubleshooting and debugging regressions, alongside reproducing functional bugs in simulation tools.
• Engaging in code reviews and possibly offering technical leadership on projects.

Requirements

Experience with testbench architecture, System Verilog, and UVM is essential. Familiarity with digital design in RTL and programming skills in C/C++, Java, or scripting languages such as Perl or Ruby are preferred. Proficiency in UNIX/Linux environments, as well as familiarity with simulation tools like VCS or Questa, is required. Knowledge of PC system architecture, particularly PCI Express, is beneficial.

Education Requirements

A Master’s or Bachelor’s degree in a relevant field with practical experience in ASIC is expected.