Design Verification Engineer

Role Summary

This position is focused on the verification of new and existing features for AMD’s graphics processor IP. The role demands the execution of verification processes to ensure a bug-free final design.

Experience Level

We are seeking candidates with a solid background in digital design and verification, along with strong analytical abilities and collaborative skills.

Responsibilities

The Design Verification Engineer will be responsible for:

• Collaborating with architects, hardware engineers, and firmware engineers on feature verification.
• Creating detailed test plans considering various interactions.
• Estimating timeframes for writing feature tests and necessary modifications to the test environment.
• Building directed and random verification tests.
• Debugging test failures and working with engineers to correct issues.
• Reviewing functional and code coverage metrics and adjusting tests as needed.

Requirements

Candidates must have:

• Proficiency in IP level ASIC verification.
• Experience debugging firmware and RTL code in simulation tools.
• Proficiency in UVM testbenches, as well as Linux and Windows environments.
• Familiarity with Verilog, System Verilog, C, and C++.
• A strong understanding of graphics pipeline concepts.
• Experience developing UVM-based verification frameworks.
• Skills in automating workflows within distributed computing environments.
• Scripting experience in languages such as Perl, Ruby, Makefile, and shell.

Education Requirements

A Bachelor's or Master's degree in Computer Engineering or Electrical Engineering is required.