Design Verification Engineer

Job Title

Design Verification Engineer

Role Summary

Senior verification engineer responsible for driving verification of server memory interfaces (DFI, DDR5, LPDDR5/LPDDR6) across DIMM products. Work on SystemVerilog/UVM-based environments and collaborate closely with hardware, firmware, BIOS, and software teams to validate system-level memory features.

Role is based in Santa Clara, CA with possible assignments in Folsom, CA and Austin, TX. Hybrid onsite/remote schedule.

Experience Level

Senior-level. The position targets experienced engineers with advanced verification skills; typical experience expectations are in the multi-year senior range as reflected in the job's academic experience guidance.

Responsibilities

Primary responsibilities include planning, implementing, and executing verification for server memory interfaces and supporting cross-functional integration and silicon bring-up.

• Define and execute verification plans for DDR5, LPDDR5, and DFI memory systems across DIMMs.
• Design and develop SystemVerilog/UVM testbenches, functional coverage, assertions, and constraints.
• Build and validate VIPs and BFMs for memory interfaces; develop simulation environments.
• Collaborate with IP/domain architects, design engineers, firmware, BIOS, and software teams on system-level memory behavior and validation requirements.
• Analyze RTL and micro-architecture to support planning and debugging activities.
• Support post-silicon teams for performance, power, and functional issue debug and resolution.
• Share verification methodology, mentor team members, and contribute to process and tool improvements.

Requirements

Must-have skills and experience required to perform the role.

Must-have:

• Advanced proficiency in SystemVerilog and UVM; experience developing verification environments and coverage models.
• Hands-on experience with DDR5, LPDDR5 and DFI memory protocols and memory subsystem verification.
• Proficiency in C/C++ and scripting languages such as Python or Perl for testbench and tooling automation.
• Strong experience with assertions, constraints, and functional coverage-driven verification.
• Ability to read and reason about RTL and engage in cross-functional debug with architects and designers.
• Excellent communication, presentation, and mentoring skills.
• This role is not eligible for visa sponsorship.

Nice-to-have:

• Experience building VIPs and BFMs from scratch.
• Experience with GLS, NLP, XPROP or similar simulation flows.
• Practical experience with formal verification tools and methodologies.
• Post-silicon validation and performance/power debug experience.

Education Requirements

Academic preference: Bachelor’s degree plus 8 years of related experience, or Master’s degree plus 6 years of related experience preferred, in a related discipline. (Posting does not specify particular fields; it refers generally to a related technical discipline.)

About the Company

Company: Advanced Micro Devices

Headquarters: Sunnyvale, California, USA

Advanced Micro Devices, or AMD, is a global semiconductor company that designs and manufactures microprocessors, graphics processors, and related technologies for a variety of computing devices. Known for pushing the boundaries of innovation, AMD's mission is to deliver high-performance computing solutions for AI, data centers, gaming, and embedded applications. They foster a collaborative, inclusive culture focused on creativity and problem-solving, aiming to drive progress and excellence in technology.