Design Verification Engineer 2

Job Title

Design Verification Engineer 2

Role Summary

Join the silicon design verification team to verify complex FPGAs and integrated IP subsystems. The role focuses on building reusable UVM testbenches, coverage-driven verification, and integrating verification environments across IP and SoC levels.

The position collaborates with design, architecture, software/firmware, and IP delivery teams to ensure tape-out readiness and product quality.

Experience Level

Mid-level — typically requires 3+ years of design verification (IP/SoC) experience.

Responsibilities

Key responsibilities include:

• Develop and maintain UVM-based testbenches, sequences, and verification infrastructure for IP and subsystem verification.
• Create IP/subsystem verification plans and portable test environments to meet coverage goals.
• Implement coverage-driven and directed test cases; analyze coverage and close verification gaps.
• Integrate multiple IP-level verification environments into larger SoC-level flows.
• Deploy and adopt verification tools and methodologies to improve tape-out readiness and productivity.
• Work with design, architecture, SW/FW, and IP teams to validate boot, power-up, and HW/FW interactions.
• Participate in debug of FPGA and SoC verification failures and support accelerated/emulation platforms as needed.
• Communicate status, risks, and verification results to cross-functional teams.

Requirements

Must-have and useful skills:

• At least 3+ years of design verification experience in IP/SoC environments, including end-to-end ASIC verification from concept to tape-out.
• Advanced hands-on knowledge of SystemVerilog and UVM methodology; demonstrated ability to deliver reusable verification IP and testbenches.
• Experience writing verification plans, developing TBs, and achieving targeted coverage metrics.
• Proven ability to collaborate with design, architecture, software/firmware, and IP teams for integration and verification.
• Strong problem-solving skills and clear communication; effective team member in cross-functional projects.
• Nice-to-have: hands-on verification experience with PCIe, Ethernet, USB, or AMBA-based IPs in UVM environments.
• Nice-to-have: exposure to low-power design flow, UPF integration, boot-up/power-cycling verification, and HW/FW interaction testing.

Education Requirements

Bachelor's or Master’s degree in Electrical Engineering, Computer Science, Computer Systems Engineering, or equivalent degree or practical experience.

About the Company

Company: Lattice Semiconductor

Headquarters: Portland, Oregon, USA

Lattice Semiconductor specializes in low power, small-form-factor programmable logic devices and solutions. The company is known for its innovative technology that enables a wide range of applications, including communication, consumer, and industrial markets.