Design Verification Engineer 2

Job Title

Design Verification Engineer 2

Role Summary

As a Design Verification Engineer II on the silicon/SoC verification team in Pune, you will plan and execute functional verification for FPGA IPs and subsystems, develop UVM-based testbenches, and drive coverage-driven verification toward tape-out readiness. The role requires close collaboration with design, architecture, firmware, and delivery teams.

Work includes building reusable verification infrastructure, integrating multiple IP DV environments, and improving verification methodologies and tools.

Experience Level

Mid-level - typically requires 3+ years of design verification experience.

Responsibilities

Primary responsibilities include:

• Develop and maintain UVM-based testbenches and verification environments for IP and subsystem verification.
• Create verification plans, directed and constrained-random tests, and coverage metrics to meet verification targets.
• Integrate IP-level DV environments into higher-level SoC verification flows.
• Verify interfaces and IPs (PCIe, Ethernet, USB, AMBA) and their interactions with firmware, boot, and power sequences.
• Work with accelerated verification platforms, verification tools, and methodologies to improve quality and efficiency.
• Collaborate with design, architecture, software/firmware, and IP delivery teams to prepare for tape-out and support silicon bring-up.
• Document verification results and support debug and root-cause analysis activities.

Requirements

Must-have and preferred skills for the role:

• Must-have: At least 3+ years of design verification (DV) experience in IP/SoC verification.
• Must-have: Proven experience across full ASIC verification flow from concept to tape-out.
• Must-have: Advanced knowledge of SystemVerilog and UVM methodology.
• Must-have: Strong communication, teamwork, and problem-solving skills.
• Nice-to-have: Hands-on verification experience with PCIe, Ethernet, USB or AMBA in UVM environments.
• Nice-to-have: Exposure to low-power design and UPF integration, power-cycling, boot-up, and HW/FW interaction verification.
• Nice-to-have: Experience with accelerated verification platforms and building portable verification infrastructure.

Education Requirements

BS or MS in Electrical Engineering, Computer Science, Computer Systems Engineering, or equivalent degree; or equivalent practical experience.

About the Company

Company: Lattice Semiconductor

Headquarters: Portland, Oregon, USA

Lattice Semiconductor specializes in low power, small-form-factor programmable logic devices and solutions. The company is known for its innovative technology that enables a wide range of applications, including communication, consumer, and industrial markets.