Design & Verification Engineer
Develop and maintain verification environments and flows for Veloce-friendly protocol test libraries (VTL) and standard protocols such as AMBA, PCIe, SAS, Ethernet, and MIPI. Work within an R&D/software verification team to ensure verification signoff through coverage-driven verification and emulation qualification.
Main mission: build robust verification environments, achieve functional and code coverage targets, and integrate/qualify VTLs with verification IPs and internal test suites.
Mid-level — 2 to 5 years of relevant verification experience.
Key responsibilities include:
Must-have technical skills and experience:
Bachelor's or Master's degree (B.Tech, M.Tech, BS, MS) in Computer Science, Electronics & Communication Engineering (ECE), Electrical Engineering (EE), Electronics & Electrical Engineering (EEE), VLSI, or related technical fields.
Company: Siemens
Headquarters: Munich, Germany
Siemens EDA is a leading global provider of Electronic Design Automation (EDA) products and systems. Their innovative solutions enable companies to enhance the development of electronic products efficiently and effectively, keeping pace with the complex demands of technology and physics. Siemens is committed to delivering advanced workflow solutions that integrate both EDA and MCAD tools for multi-domain design and manufacturing in the semiconductor industry.
