Design Implementation Engineer

Job Title

Design Implementation Engineer

Role Summary

Responsible for physical implementation and timing closure of ASIC/SoC designs across block and full‑chip flows. Work includes floor‑planning, placement, clock tree synthesis, routing, timing analysis and closure, physical verification, equivalence checks and ECO implementation.

Role operates within a hardware design team following established design methodology and milestone flows to achieve first‑time silicon success.

Experience Level

Senior - role expects substantial industry experience (see Education Requirements for years-of-experience guidance).

Responsibilities

Primary technical duties and delivery expectations:

• Perform place-and-route and timing closure at block and full‑chip levels (floor‑planning, partitioning, placement, CTS, routing).
• Develop and validate constraints, run static timing analysis and drive timing closure.
• Implement functional and timing ECOs and run equivalence checks.
• Run and troubleshoot physical verification (LVS/DRC) and signoff flows.
• Optimize for power, performance and area (PPA) using established tools and methodologies.
• Drive tool flows and collaborate with cross‑functional and global teams to meet tapeout milestones.

Requirements

Must-have technical skills and attributes:

• Hands‑on experience with timing analysis and place-and-route tools for ASIC/SoC design.
• Proven expertise in floor‑planning, placement, clock tree synthesis, routing, constraints development/validation, timing analysis and closure.
• Experience implementing timing and functional ECOs and performing equivalence checks.
• Full‑chip tapeout experience on 7nm or smaller process nodes; ideally participated in 1–2 tapeouts.
• Strong problem solving, self‑starter attitude, and effective written/verbal communication.
• Ability to learn and adopt new tools and methodologies quickly and work in a global team environment.

Nice-to-have:

• Experience with tools such as Synopsys PrimeTime, ICC2, Cadence Innovus, Mentor Calibre, LEC or similar signoff and P&R tools.
• Formal verification or advanced STA tooling experience.

Education Requirements

BS in Electrical Engineering, Computer Engineering or related field with 8+ years of relevant experience, OR MS in Electrical Engineering, Computer Engineering or related field with 6+ years of relevant experience. Equivalent practical experience considered.

About the Company

Company: Broadcom

Headquarters: Irvine, California, United States

Broadcom is a global technology leader that designs, develops, and supplies a wide range of semiconductor and infrastructure software solutions. The company is known for its innovations in wireless and broadband communications, enabling a connected world.