Design for Testability (DFT) Engineer

Job Title

Design for Testability (DFT) Engineer

Role Summary

Hands-on DFT engineer on a semiconductor SoC team in the Bay Area responsible for defining, implementing, and verifying DFT architectures for advanced-node SoCs targeting AI, automotive, networking, and next-gen compute.

The role covers DFT architecture, ATPG and fault-coverage optimization, MBIST/LBIST insertion and verification, timing-aware pattern simulation, and silicon bring-up/ATE support.

Experience Level

Mid-level - typically requires 3+ years of hands-on DFT implementation and verification on complex ASIC/SoC designs.

Responsibilities

Practical, delivery-focused responsibilities for DFT implementation, verification, and silicon support.

• Define and implement DFT architectures: scan insertion, compression, ATPG integration, MBIST/LBIST controllers, and relevant IEEE standards (1149.1, 1500, 1687/IJTAG, 21686).
• Generate, debug, and optimize ATPG patterns (stuck-at, at-speed/transition, cell-aware, path-delay) to meet fault-coverage targets.
• Insert and verify MBIST/LBIST across multi-frequency clock domains and multi-die / chiplet architectures.
• Run zero-delay and SDF timing-annotated pattern simulations; debug timing violations and coordinate with Physical Design for DFT constraints and STA closure.
• Support silicon bring-up and ATE activities: pattern translation (WGL/STIL), failure analysis, and lab validation.
• Collaborate with cross-functional teams (PD, product, test engineering) and produce clear diagnostics and documentation for yield and failure analysis.

Requirements

Must-have technical skills and practical experience.

• 3+ years of hands-on DFT implementation and verification on complex ASIC/SoC designs.
• Strong proficiency in at least one major DFT/ATE EDA suite (examples: Siemens/Mentor Tessent, Synopsys TestMAX, Cadence Modus).
• Experience with ATPG workflows and tools; familiarity with stuck-at, at-speed, cell-aware, and path-delay test generation and fault-coverage analysis.
• Practical experience with MBIST/LBIST insertion and verification.
• Experience with pattern simulation and timing-aware verification (SDF), and working knowledge of STA interactions for DFT closure.
• Programming/scripting skills for flow automation (TCL, Perl, Python, Bash).
• Proficiency in hardware description languages: Verilog, SystemVerilog, and VHDL.
• Hands-on experience supporting silicon bring-up, ATE pattern validation, and failure analysis in a lab/test-house environment.
• Effective communication and teamwork skills to coordinate with PD, test, and product teams.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Microelectronics, or a related technical field.

Preferred Qualifications

Nice-to-have skills that increase impact in this role.

• Experience with advanced process nodes (5nm, 3nm, 2nm) and multi-die / 2.5D / 3D chiplet architectures.
• Deep understanding of fault diagnostics, yield-learning workflows, and failure analysis methodologies.
• Familiarity with automotive functional safety and ISO 26262-related DFT mechanisms.

About the Company

Company: Info Way Solutions

A technology staffing and recruitment firm that posts engineering and IT job opportunities; in this posting they represent L&T Technology Services for a DFT Engineer role.