Design for Test Lead

Job Title

Design for Test Lead

Role Summary

The Design for Test (DFT) Lead owns DFT architecture and delivery for Neurophos' electronic ASICs. You will set the chip-level DFT strategy, drive coverage assessment and signoff, integrate testability into RTL and physical design, and lead the handoff to post-silicon and production test teams.

This is the company's first dedicated DFT hire: you will define DFT processes, work with digital and analog teams, and grow the DFT capability. The role is full-time onsite in Austin, TX or Sunnyvale, CA.

Experience Level

Senior - typically 8–15 years of DFT or related ASIC test/verification experience, with architect-level ownership of DFT on large digital ASICs.

Responsibilities

Primary responsibilities include defining DFT strategy, implementing test features across design phases, and owning coverage and production test delivery.

• Define and own DFT architecture and test-control design for multiple ASICs using ATPG scan (stuck-at/at-speed), MBIST, and boundary scan/JTAG.
• Include DFT capabilities for MCM and external HBM memory modules.
• Architect on-die memory test: controller specification/generation, pattern selection, RAM grouping, and system test time/power analysis.
• Ensure implementation of test modes required for product qualification (e.g., HAST) with operations and product engineering.
• Plan wafer- and package-level DFT across product development phases.
• Create and deploy an integrated DFT development flow with metrics to drive near-100% coverage improvements.
• Own coverage assessment and signoff, documenting accepted coverage gaps and rationale.
• Develop and specify functional test vectors to supplement structural coverage.
• Specify analog test requirements (self-test, loopback) and coordinate with the analog team.
• Integrate testability into RTL and implementation early, and manage handoff to post-silicon and OSAT production test programs.

Requirements

Must-have technical experience and skills for immediate impact; preferred items listed separately.

• 8–15 years of DFT experience with hands-on ownership of scan, ATPG, and MBIST.
• Architect-level responsibility on a large digital ASIC: defined DFT strategy and owned coverage signoff.
• Proven track record through tapeout on complex compute ASICs.
• Experience developing and specifying functional test vectors to augment structural coverage.
• Ability to define test requirements for analog circuits and collaborate with analog/physical teams.
• Experience working with operations, packaging, and production test partners (OSATs).
• Strong communication skills to set DFT policy and document coverage decisions.

Education Requirements

Not specified.

Preferred Skills

Nice-to-have skills that will accelerate success in the role.

• Experience with Cadence toolchain and DFT tool flows.
• Exposure to silicon photonics test or DFT for photonic components.
• Experience using AI tooling in DFT flows.

About the Company (brief)

Neurophos develops silicon-photonics-based AI inference hardware that uses programmable metasurfaces to improve energy efficiency and performance for large-scale AI inference.

What We Offer

Competitive compensation and benefits including health coverage, unlimited PTO, 401(k) matching, stock options, and a suite of voluntary benefits.

About the Company

Company: Neurophos

Headquarters: Sunnyvale, California, United States

Startup developing silicon-photonic AI accelerator chips that use programmable metasurfaces and dense optical cells to perform matrix multiplications at the speed of light, targeting large-scale AI inference with much higher energy efficiency and performance than traditional electronic approaches.