Design For Test Engineer IV (IC)
eInfochipsJob Title
Design For Test Engineer IV (IC)
Role Summary
Engineer responsible for design-for-test (DFT) implementation and verification for advanced-node (3nm/5nm) networking SoCs and IP blocks. Work includes scan insertion, ATPG, pattern simulation, MBIST and JTAG insertion, silicon debug and flow automation.
Position is on-site and interfaces with RTL, design IP teams, verification and bring-up teams to ensure testability and test coverage for complex multi-million gate designs.
Experience Level
Mid-level — approximately 5–7 years of relevant DFT experience.
Responsibilities
Primary responsibilities include test insertion, pattern generation, simulation, and automation for SoC and IP designs.
- Implement DFT for 3nm and 5nm networking chips and IP blocks.
- Perform RTL checks for scan-insertion compatibility using static analysis tools.
- Execute scan-insertion flows (Mentor Tessent TestKompress).
- Generate ATPG patterns (compressed and uncompressed) using Tessent, Cadence Modus, and Synopsys Tetramax.
- Run pattern simulations with and without timing (using VCS) across corners.
- Debug mismatches and failures using debug tools (e.g., Verdi).
- Insert and verify MBIST at block and top levels; support silicon bring-up and debug.
- Insert and verify IEEE 1149.1 JTAG.
- Develop and maintain flow automation, scripts (Perl, Shell, TCL) and Makefile targets to improve DFT flows.
Requirements
Required skills and experience. Must-haves listed first; then concise nice-to-have items.
- 5–7 years of hands-on DFT experience (scan insertion, ATPG, GLS, pattern simulation).
- Experienced with MBIST insertion/verification and IEEE 1149.1 JTAG insertion and verification.
- Proficient in scripting (Perl, Shell, TCL) and flow automation.
- Experience with Mentor Tessent; familiarity with Cadence Modus and Synopsys Tetramax is useful.
- Worked on multi-million gate SoCs and IPs (networking, consumer; PLL, SerDes).
- Experience with pattern simulation (with and without timing) and silicon bring-up/debug.
- Strong verbal and written communication skills.
- Knowledge of low-power DFT techniques.
Education Requirements
B.Tech or M.Tech in Microelectronics, Electronics or closely related fields (B. Tech, M.Tech). No certifications specified; equivalent technical education or experience may be considered if documented.
About the Company
Company: eInfochips
Headquarters: Bengaluru, India
eInfochips is a product engineering and semiconductor design services company offering embedded software, SoC design and verification, testing, and IoT solutions. It operates as part of Arrow Electronics, serving clients across industries worldwide.
