Design For Test Engineer

Job Title

Design For Test Engineer

Role Summary

On-site DFT engineer responsible for implementing testability and test infrastructure for advanced-node (3nm/5nm) networking SoCs and IP blocks. The role focuses on scan insertion, ATPG, pattern simulation, MBIST and JTAG insertion, plus test flow automation and silicon bring-up while working at the client office in San Jose.

Experience Level

Mid-level — 5 to 7 years of DFT experience (networking SoCs and related IP).

Responsibilities

Primary technical responsibilities and deliverables for the role.

• Implement DFT for 3nm and 5nm networking chips and associated IP blocks.
• Perform RTL checks for scan-insertion compatibility using Synopsys Spyglass.
• Perform scan-insertion using Mentor Tessent (TestKompress).
• Generate ATPG patterns in compressed and uncompressed modes using tools such as Mentor Tessent, Cadence Modus, and Synopsys Tetramax.
• Run pattern simulation with and without timing across corners (using VCS).
• Debug mismatches and test failures using Verdi.
• Develop and maintain automation and flows using Perl, Shell, and Tcl; enhance DAeRT DFT flow and Makefiles.
• Insert and verify MBIST at block and top levels; support silicon debug and bring-up for blocks and top-level integration.
• Insert and verify IEEE 1149.1 JTAG.

Requirements

Must-have technical skills and experience; concise distinction of required versus desirable skills.

• Must-have: 5–7 years of DFT experience including scan-insertion, ATPG, and pattern simulation (with and without timing).
• Must-have: MBIST insertion and verification; IEEE 1149.1 JTAG insertion and verification.
• Must-have: Scripting and automation experience with Perl, Shell, and Tcl; experience improving DFT flows and Makefiles.
• Must-have: Experience on multi-million-gate SoCs and IPs (networking domain; examples: PLLs, SerDes).
• Must-have: Experience with Mentor Tessent (TestKompress) for scan and ATPG.
• Must-have: Effective verbal and written communication skills.
• Nice-to-have: Familiarity with Cadence Modus, Synopsys Tetramax, VCS, Verdi, low-power DFT techniques, and silicon bring-up/debug experience.

Education Requirements

B.Tech or M.Tech in Microelectronics or Electronics (as listed). No other degrees or equivalent-experience language specified in the posting.

About the Company

Company: eInfochips

Headquarters: Bengaluru, India

eInfochips is a product engineering and semiconductor design services company offering embedded software, SoC design and verification, testing, and IoT solutions. It operates as part of Arrow Electronics, serving clients across industries worldwide.