Design for Test (DFT) Engineer

Job Title

Design for Test (DFT) Engineer

Role Summary

Senior DFT engineer to establish and lead the DFT function for a leading-edge multi-die packaged SoC, working across architecture, RTL insertion, ATPG/pattern generation, verification, silicon bring-up, and production test. Partner closely with design, verification, physical design, and product/test engineering to deliver testable, yield-ready silicon.

Primary focus: define test-access architecture for a multi-die package and build an automated DFT flow integrated into the RTL-to-GDSII methodology.

Experience Level

Senior — typically 7+ years of hands-on DFT/ASIC experience.

Responsibilities

Design, implement, verify, and operationalize DFT for multi-die packaged silicon across the full flow.

• Architect and implement test-access for multi-die packages: post-package scan access, KGD sorting, D2D interconnect test, and package-level test-access architecture.
• Develop and maintain the end-to-end DFT flow: insertion, ATPG/pattern generation, verification, coverage closure, and signoff.
• Implement DFT structures including scan (stuck-at, transition/at-speed), compression, boundary-scan (JTAG/1149.x), and IEEE 1500 core wrapping.
• Implement and verify Memory BIST, including external/shared MBIST controller integration and verification.
• Drive ATPG, fault simulation, pattern conversion/porting to ATE formats (STIL/WGL), and design-to-tester handoff.
• Perform DFT verification: scan-chain integrity, pattern verification, gate-level simulation with timing (SDF), and coverage analysis.
• Support silicon bring-up, debug, failure analysis, and correlation of ATE results to design.
• Collaborate with PD on scan stitching, test-point insertion, timing, and power-aware test; document and automate methodology.

Requirements

Core technical skills, tooling expertise, and practical DFT execution experience required to lead and scale a DFT function.

• Must-have: 7+ years hands-on DFT engineering on complex digital SoC/ASIC designs with breadth across architecture, insertion, ATPG, BIST, boundary-scan, verification, and silicon test.
• Must-have: Experience building, automating, and maintaining DFT flows (not just running tools).
• Must-have: Hierarchical/core-wrapping DFT experience and block-level test architecture implementation.
• Must-have: Strong Siemens Tessent experience: Scan & ATPG (TestKompress), MemoryBIST, BoundaryScan/IJTAG.
• Must-have: ATPG and fault simulation knowledge (stuck-at, transition/path-delay), compression, coverage closure, and pattern verification.
• Must-have: Gate-level simulation of test modes, scripting for flow automation (Tcl, Python, Perl), and familiarity with RTL (Verilog/SystemVerilog) and SDC.
• Must-have: Familiarity with ATE pattern formats (STIL/WGL) and the design-to-tester handoff.
• Preferred: Low-power DFT experience (UPF/CPF, power-aware ATPG, retention/isolation test) and experience with advanced-package/multi-die test challenges.

Education Requirements

Bachelor's or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical field (BS/MS). Equivalent practical experience in DFT/ASIC engineering may be acceptable.

About the Company

Company: DensityAI

Headquarters: Mountain View, CA, United States

DensityAI is a semiconductor company focused on developing advanced silicon and multi-die packaged chips, with expertise in design-for-test, verification, and production test for high-performance and AI applications.