Design for Test (DFT) Engineer

Job Title

Design for Test (DFT) Engineer

Role Summary

Responsible for developing and implementing testability solutions for complex digital ASICs, SoCs, and modern processors. The role partners with design, verification, and test engineering teams to ensure testability is addressed across the product development lifecycle.

Work includes DFT architecture and implementation, testability analysis, methodology development, DFT verification, and test pattern generation for mission-critical hardware.

Experience Level

Mid-level. Typical experience guidance from the posting: 5–7 years with a Bachelor's degree, 3–5 years with a Master's degree, or 0–2 years with a PhD.

Responsibilities

Typical responsibilities include:

• Architect and implement DFT solutions for digital ASICs and SoCs, including DFT insertion and test access mechanisms.
• Perform testability analysis and develop DFT methodology and verification flows.
• Generate and validate test patterns and support test pattern generation activities.
• Design and simulate circuits at the transistor level to meet architecture and requirement specifications.
• Contribute to system-level design and optimize hardware for performance, power, and cost.
• Evaluate hardware feasibility of complex algorithms and requirements and drive technical solutions.
• Perform or guide physical layout activities including floor-planning and simulation with extracted parasitics.
• Document and teach best practices; contribute to proposals and business development as needed.

Requirements

Must-have skills and conditions:

• Proven experience in DFT for digital ASICs, SoCs, or processors, including DFT architecture, insertion, and verification.
• Experience with transistor-level circuit design and simulation.
• Experience with test pattern generation and DFT verification flows.
• Hands-on familiarity with floor-planning and physical-layout considerations relevant to testability.
• Strong analytical and problem-solving skills, attention to detail, and ability to prioritize tasks to meet deadlines.
• Effective verbal and written communication skills and experience mentoring or leading small technical teams.
• Ability to obtain and maintain a U.S. government security clearance (required for hire).

Nice-to-have:

• Experience with state-of-the-art processors and complex SoC architectures.
• Proposal, business development, or cross-functional program experience.

Education Requirements

Requires a Bachelor's degree in Engineering or a related field; a Master’s degree is preferred and a PhD is acceptable. The posting specifies experience equivalencies: 5–7 years with a Bachelor's, 3–5 years with a Master’s, or 0–2 years with a PhD in ASIC hardware engineering or a related discipline.

About the Company

Company: Draper

Headquarters: Cambridge, MA, United States

Draper is an independent, nonprofit research and development organization based in Cambridge, Massachusetts. With over 2,000 employees, Draper develops advanced technologies in defense, space, biomedical engineering, and other national-security and commercial domains through multidisciplinary teams of engineers and scientists.