Design Engineering Architect

Job Title

Design Engineering Architect

Role Summary

The Design Engineering Architect will lead RTL/IP architecture and implementation for Cadence's Controller IP team based in Cork. The role defines micro-architecture and specifications for high-speed interfaces (for example UCIe, Ethernet, HBM, PCIe), drives RTL development through sign-off, and coordinates across product, analog, and software teams to deliver production-quality IP.

This position is hands-on and involves standards representation and engagement with customers and industry bodies.

Experience Level

Senior — typically 15–20 years' experience in the microelectronics industry, with proven technical team leadership.

Responsibilities

Primary responsibilities include technical leadership, hands-on RTL delivery, and cross-functional coordination.

• Provide technical leadership for complex IP such as UCIe, Ethernet, HBM and PCIe.
• Collaborate with system architects and product managers to define architecture and specifications for standards (e.g., UCIe), considering data rate, power, and standards compatibility.
• Lead hands-on RTL development from micro-architecture definition through IP sign-off for general release.
• Plan activities and milestones for digital development teams.
• Lead cross-functional technical meetings with Analog and Software counterparts.
• Support customer pre-sales and post-sales technical engagements.
• Develop and improve processes for efficient product execution and IP quality.
• Participate in Technical Review Meetings and Checklist Reviews in support of ISO-9001 processes.
• Represent Cadence in standards-body working groups (for example IEEE, PCI-SIG, JEDEC, UCIe) and present at industry conferences.
• Travel: under 10%.

Requirements

Must-have and preferred technical skills and experience.

• Must-have: 15–20 years' experience in the microelectronics industry with technical leadership experience.
• Must-have: Expert Verilog/SystemVerilog RTL design.
• Must-have: Expert with front-end design tool flow: LINT, synthesis, CDC/RDC analysis.
• Must-have: Experience with SoC architecture and development.
• Must-have: Excellent oral and written English; strong planning and interpersonal skills; ability to communicate complex concepts clearly.
• Nice-to-have: Metric Driven Verification (MDV) and UVM experience.
• Nice-to-have: Experience with industry standard protocols such as AXI, CHI-C2C, and CXS.B.
• Nice-to-have: Experience with quality processes such as ISO-9001 and ISO-26262.

Education Requirements

Degree in Electrical/Electronic Engineering, microelectronics, or a related discipline.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.