Design Engineer - STA

Job Title

Design Engineer - STA

Role Summary

Senior static timing analysis (STA) engineer responsible for timing closure and signoff for ASIC/VLSI designs. Works with physical design, RTL, and signoff tool flows to create and validate timing constraints, analyze timing reports, and resolve timing issues across multi-team, multi-timezone projects.

Role involves independent technical judgment, cross-team coordination, and occasional supervision or mentoring of other engineers.

Experience Level

Senior — typically 10+ years of relevant industry experience (examples in posting: MS +10 years or BS +12 years).

Responsibilities

Primary duties and scope of work:

• Perform static timing analysis for digital ASIC/VLSI designs using industry signoff tools.
• Create, debug and maintain timing constraints and timing decks; generate and interpret timing reports.
• Analyze setup, hold, and other timing checks; produce timing diagrams and root-cause analyses.
• Evaluate RC networks, signal integrity, crosstalk delay, and glitch/noise impacts on timing.
• Investigate and resolve tool warnings/errors and timing signoff issues.
• Collaborate with physical design, RTL teams, and cross-functional engineers across geographies to achieve timing closure.
• Manage and organize large datasets related to timing signoff and present data clearly to stakeholders.
• May supervise or mentor other engineers and help define methods for new assignments.

Requirements

Must-have technical skills and experience (concise):

• Strong understanding of VLSI and ASIC physical design concepts (placement, routing, timing effects).
• Experience with static timing analysis tools (preferably Synopsys PrimeTime and/or Cadence Tempus).
• Ability to create and debug timing constraints and interpret timing reports and tool messages.
• Practical knowledge of setup and hold analysis, timing diagrams, and RC network effects on timing.
• TCL scripting required; experience with one or more additional languages (Python, Ruby, Bash) preferred.
• Strong debugging skills, engineering judgment, and clear written/verbal communication across distributed teams.

Nice-to-have:

• Experience with advanced STA concepts: POCV/SOCV/LVF, MIS, CCS/ECSM/NLDM models, PBA, LOCV/SOCV timing derates.
• Experience on SOIC/3DIC timing designs and SPICE analysis.

Education Requirements

BS in Electrical Engineering or Computer Engineering with 12+ years related experience, or MS in Electrical Engineering or Computer Engineering with 10+ years related experience (degrees and years specified in the posting).

About the Company

Company: Broadcom

Headquarters: Irvine, California, United States

Broadcom is a global technology leader that designs, develops, and supplies a wide range of semiconductor and infrastructure software solutions. The company is known for its innovations in wireless and broadband communications, enabling a connected world.