Design Engineer I
Cadence Design SystemsJob Title
Design Engineer I
Role Summary
Perform post-silicon validation and system interoperability testing for high-speed SerDes PHYs. Work on lab-based debug, compliance and system-level verification to ensure protocol and electrical correctness.
Member of a validation team based in Bangalore, collaborating with FPGA, firmware, and RTL engineers to reproduce, debug and resolve PHY and interoperability issues across PCIe/CXL/UCIe/Ethernet interfaces.
Experience Level
Entry-level (Engineer I). The posting indicates experience expectations that vary by degree; see Education Requirements for degree-specific guidance.
Responsibilities
Key responsibilities include hands-on validation, test development, and team mentoring.
- Plan and execute post-silicon PHY, system interoperability and compliance tests for high-speed SerDes solutions.
- Perform lab debug using oscilloscopes, bit-error-rate testers, protocol exercisers and analyzers.
- Develop FPGA prototypes, testbenches and schematic-level tests to reproduce issues.
- Lead or mentor small engineering teams and coordinate system testing efforts.
- Document test results, file and track issues, and work cross-functionally with RTL, firmware and hardware teams to close bugs.
Requirements
Must-have technical skills and preferred experience.
- Must-have: Practical experience with physical and protocol layers on at least one high-speed SerDes (PCIe, CXL, UCIe or Ethernet).
- Hands-on debug experience with lab instruments: oscilloscopes, BER testers, protocol exercisers/analyzers.
- 2–3 years experience leading or mentoring a small team of engineers.
- Experience developing FPGA designs and schematics; familiarity with Verilog for FPGA work.
- Proficiency in scripting and programming for tests: Python and C/C++.
- Strong written and verbal communication skills.
- Nice-to-have: Experience with PCIe/UCIe LTSSM states and IP/SoC physical-layer electrical validation.
Education Requirements
Posting explicitly references BTech and MTech: 2–10 years of relevant post-silicon PHY, systems interop and compliance testing experience for candidates holding a BTech, or 8 years for candidates holding an MTech. No other degrees, specific fields of study, certifications or explicit "equivalent experience" language were provided.
About the Company
Company: Cadence Design Systems
Headquarters: San Jose, California, USA
Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.
