Design Engineer

Job Title

Design Engineer

Role Summary

Lead and execute analog / mixed-signal IC layout projects, working with circuit designers and junior layout engineers to deliver tape-out ready blocks. The role focuses on physical layout creation, verification, and application of analog layout techniques to minimize parasitics and ensure manufacturability.

Experience Level

Mid-level — typically 3–5 years of relevant Analog IC layout design experience.

Responsibilities

Primary responsibilities include hands-on layout work, verification, and project coordination to meet tape-out schedules.

• Lead and mentor junior layout engineers and coordinate with circuit designers and process teams.
• Create and edit cell- and block-level layouts using EDA tools (Cadence, Synopsys) and perform full verification.
• Apply analog layout techniques for matching, ESD and latch‑up prevention, substrate noise control, and parasitic reduction.
• Use schematic-driven layout flows and consider top-level auto‑routing where appropriate.
• Prepare layout data and documentation for wafer tape-out and participate in review sessions.
• Attend project meetings, track schedule risks, and report progress.

Requirements

Must-have technical skills, experience, and work conditions.

• Minimum 3–5 years in Analog IC layout design; experience with mixed-signal layouts and size optimization.
• Expertise with Cadence Virtuoso and Synopsys tools for layout and physical verification.
• Experience with layout techniques for matching, shielding, guard-rings, and substrate-noise control.
• Hands-on knowledge of CMOS devices, including high-voltage devices, and familiarity with design manuals.
• Ability to perform physical verification and awareness of EM/IR and power/ground optimization.
• Good verbal and written communication skills in English; strong collaboration and cross-team communication.
• Willingness to work onsite in Bayan Lepas and to support teams across different time zones; willing to relocate if required.
• At least 1 year experience in a product sub-lead or leadership role (project delivery responsibility).

Nice-to-have

• Experience with ADC/DAC, LDO, Bandgap, PMIC block layouts.
• Familiarity with Calibre or equivalent physical verification flows.
• Ability to write SKILL, Python, or TCL scripts to automate layout checks or flows.
• Japanese language skills are a plus.

Education Requirements

Bachelor's degree in Electrical/Electronic Engineering, Physics, Computer Engineering/Science, or a related field is required.

Additional Information

Employer: Renesas. Role is onsite in Bayan Lepas, Malaysia and focuses on analog IC layout for semiconductor products.

About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.