Design Architect
Cadence Design SystemsJob Title
Design Architect
Role Summary
Senior engineering role on a team developing high-performance physical IP (SerDes portfolio). Responsible for digital architecture, micro-architecture, RTL implementation, and tool-flow execution to ensure IP quality across power, performance, and area targets.
Experience Level
Senior — 18–20 years of experience expected.
Responsibilities
Primary responsibilities include architecture-to-RTL delivery, low-power and synthesis considerations, and collaboration across verification and analog teams.
- Define digital architecture and drive it to micro-architecture and RTL implementation.
- Balance trade-offs for power, performance, and area during design decisions.
- Create synthesis constraints and SDC, and support timing analysis flows.
- Design and specify low-power features (power islands, state retention, isolation).
- Work with verification to define coverage, test strategies, corner conditions, and stimulus.
- Integrate and validate embedded microcontroller-based subsystems.
- Execute and refine IP quality-control tool flows and design automation scripts.
- Collaborate with mixed-signal, analog, verification, and global project teams.
Requirements
Key qualifications and skills required or preferred.
Must-have:
- 18–20 years of experience in digital design and architecture for semiconductor IP.
- Proven experience in design architecture and implementation for high-performance IP.
- Experience with synthesis and SDC creation; familiarity with timing analysis.
- Experience with embedded microcontroller designs and integrating uC-based subsystems.
- Experience scripting design automation and debugging verification test cases / SVA.
- Knowledge of serial standards such as PCIe, USB, Ethernet or similar.
- Strong cross-functional written and verbal communication; able to work with mixed-signal, analog, and verification teams.
Nice-to-have:
- Familiarity with AI-assisted design practices and AI-assisted design flows.
- Experience with SystemVerilog, Python, C/C++.
- Working knowledge of revision control tools (Perforce, Git, SVN).
Education Requirements
Minimum Bachelor's degree required; Master’s degree preferred. No specific field of study listed.
About the Company
Company: Cadence Design Systems
Headquarters: San Jose, California, USA
Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.
