DDR Pre-Silicon Verification Architect

Job Title

DDR Pre-Silicon Verification Architect

Role Summary

Perform pre-silicon functional verification of DDR and mixed-signal IP, developing verification plans, testbenches, and environments to validate microarchitecture, functional correctness, performance, and power targets.

The role works within an engineering verification team and collaborates with digital and analog architects, RTL developers, and physical design teams to find, reproduce, and resolve issues before silicon.

Experience Level

Senior level — requires substantial industry experience (see Education Requirements for specific years-of-experience guidance).

Responsibilities

Primary responsibilities include planning, implementing, executing, and improving pre-silicon verification for DDR IP and related subsystems.

• Develop IP verification plans, testbenches, verification environments, BFMs, and checkers.
• Implement UVM/SystemVerilog test environments and integrate with simulation tools.
• Create and run system-level simulations to verify functionality, timing, and power; analyze results.
• Replicate, root-cause, and debug issues in the presilicon environment and implement fixes or workarounds.
• Collaborate with architects, RTL designers, and physical design teams to validate complex microarchitectural features.
• Document test plans and drive technical reviews with design and architecture teams.
• Maintain and improve functional verification infrastructure and methodologies.

Requirements

Required and desirable technical skills and domain experience for successful performance in this role.

• Must-have: Hands-on IP verification experience using Verilog/SystemVerilog and UVM; experience developing verification environments and testbenches.
• Must-have: Strong knowledge of DDR protocols (DDR4/DDR5/LP5/LP6) and experience verifying DDR IP.
• Must-have: Simulation and debug experience with industry tools (examples: VCS, Verdi).
• Experience with coverage-driven verification, assertions, and checker development.
• Experience integrating BFMs/checkers and validating subsystem-to-SoC integration.
• Nice-to-have: Low-power design verification using UPF and clock gating; multiple clock domain design experience.
• Nice-to-have: Exposure to mixed-signal verification and GLS verification.
• Ability to write clear test plans and test cases and to drive technical reviews.

Education Requirements

BE/B.Tech with 12 years of relevant industry experience OR ME/M.Tech with 10 years of relevant industry experience. (No alternate-equivalent wording provided.)

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.