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DDR PHY System Design Engineer

Qualcomm
August 31, 2026
Full-time
On-site
San Diego, California, United States
$140,000 - $210,000 USD yearly
Semiconductor IP Jobs, Level - Mid-Career

Job Title

DDR PHY System Design Engineer

Role Summary

Design and architect high-speed DDR PHY systems for mobile, compute, AI/ML, 5G, and automotive products. Work within the mixed-signal IP DDR PHY team to develop system timing, link training, and validate designs from concept through production.

Experience Level

Mid-level. Typical candidate has 5–10 years of hands-on DDR PHY system design or architecture experience; equivalent experience considered per education level (see Education Requirements).

Responsibilities

Accountable for system-level DDR PHY architecture, timing, and validation across product development stages.

  • Define and own DDR PHY system and architecture for product requirements.
  • Develop on-die and off-chip system timing budgets and verify timing closure.
  • Specify and validate link budgets and training procedures for DRAM interfaces.
  • Collaborate with signal-integrity, power-delivery, and mixed-signal teams to meet performance and yield targets.
  • Lead cross-functional design reviews and coordinate activities across global teams.
  • Support bring-up, production validation, and problem resolution for high-speed links.

Requirements

Core technical skills and experience required; preferred skills that improve fit are listed separately.

  • Must-have — 5–10 years of DDR PHY system design or architecture experience focused on high-speed memory interfaces.
  • Must-have — Strong knowledge of JEDEC DDR standards (LPDDR, PCDDR, HBM) and their system implications.
  • Must-have — Demonstrated experience with link budgets, training algorithms, and validating high-speed links.
  • Must-have — Strong written and verbal communication; proven ability to coordinate across global engineering teams.
  • Nice-to-have — Signal integrity and power-delivery experience for server-class products.
  • Nice-to-have — Familiarity with advanced process nodes and mixed-signal design constraints.
  • Nice-to-have — Understanding of design-for-yield, production challenges, and reliability for high-speed links.
  • Nice-to-have — Scripting experience (Unix/Perl/Tcl) and comfort automating analysis tasks.

Education Requirements

Required: Bachelor's degree in Electrical Engineering (or related science/engineering field). Preferred: Master’s degree in Electrical Engineering. Qualcomm also lists degree/experience equivalencies: Bachelor’s + 4+ years relevant ASIC design/verification/validation/integration experience; Master’s + 3+ years; PhD + 2+ years. Equivalent practical experience will be considered where specified.


About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.

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Date Posted: 2026-08-31