Custom SOC IP Verification Engineer

Job Title

Custom SoC IP Verification Engineer

Role Summary

Verify fabric and interconnect IP and SoC integrations for high-performance custom SoCs. The role focuses on correctness, performance, and protocol compliance of on-chip fabrics from IP bring-up through full-chip integration.

Work closely with architecture, design, software/firmware, modeling, emulation, and post-silicon teams to deliver robust verification plans and execute them in UVM/SystemVerilog environments.

Experience Level

Senior — 5+ years of ASIC verification experience, with a strong focus on fabric, interconnect, or network-on-chip verification at both IP and full-chip levels.

Responsibilities

Primary verification responsibilities for interconnect and fabric subsystems:

• Plan and execute ASIC verification for fabric and interconnect IP and full-chip integration (DMA, routing, arbitration, ordering, flow control, protocol compliance).
• Develop and implement test plans and UVM-based verification environments for IP- and system-level scenarios.
• Design and implement constrained-random and directed SystemVerilog testbenches targeting interconnect fabrics, NoC topologies, and multi-agent SoC integrations.
• Collaborate with Architecture, SW/FW, Design, Modeling, Emulation, and Post-Silicon Validation to ensure comprehensive verification coverage and first-time-right silicon.
• Drive silicon and platform verification strategies and methodologies for fabric and interconnect subsystems.
• Support performance analysis and validation (bandwidth/latency) as part of verification sign-off.

Requirements

Required skills and experience; separates must-have from nice-to-have items.

• Must-have: 5+ years of ASIC verification experience with emphasis on fabric, interconnect, or NoC verification at both IP and full-chip levels.
• Must-have: Strong SystemVerilog and UVM methodology expertise.
• Must-have: Hands-on experience with interconnect and bus protocols (e.g., AMBA AXI, CHI, or equivalent) and a solid understanding of ordering, coherency, and flow-control semantics.
• Must-have: Familiarity with SoC architectures, NoC topologies, and multi-initiator/multi-target interconnect designs.
• Must-have: Proficiency in scripting (Python, Perl, TCL) for testbench and flow automation.
• Nice-to-have: Performance verification and bandwidth/latency analysis experience for interconnect fabrics.
• Nice-to-have: Exposure to verification IPs for bus protocols or emulation platforms (e.g., Palladium, Veloce) for full-chip validation.
• Nice-to-have: Experience with GPU or AI-accelerator SoC interconnect verification, formal verification, or assertion-based verification (SVA).

Education Requirements

B.S. or M.S. in Computer Engineering, Electrical Engineering, or a related field, or equivalent practical experience.

About the Company

Company: NVIDIA

Headquarters: Santa Clara, California, USA

NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.