Custom SOC IP Verification Engineer

Job Title

Custom SOC IP Verification Engineer

Role Summary

Verify fabric and interconnect IP blocks and their full-chip integration to ensure correctness, performance, and protocol compliance from IP bring-up through system-level silicon.

Work on ASIC verification using SystemVerilog/UVM and collaborate with architecture, design, software/firmware, modeling, emulation, and post-silicon teams to deliver robust, high-performance SoC connectivity.

Experience Level

Senior-level — typically 5+ years of ASIC verification experience focused on fabric, interconnect, or NoC verification.

Responsibilities

Primary responsibilities include planning and executing verification activities for fabrics, interconnects, and their integration into SoCs.

• Verify fabric and interconnect IP blocks and full-chip integration covering DMA, routing, arbitration, ordering, flow control, and protocol compliance.
• Develop and implement UVM-based test plans for IP- and system-level fabric/interconnect verification.
• Design and implement constrained-random and directed SystemVerilog testbenches for interconnect fabrics, NoC topologies, and multi-agent SoC integrations.
• Collaborate with Architecture, SW/FW, Design, Modeling, Emulation, and Post-Silicon Validation teams to achieve first-time-right verification.
• Define and drive silicon and platform verification strategies and methodologies for fabric and interconnect subsystems.

Requirements

Must-have technical skills and experience.

• 5+ years of ASIC verification experience with a strong focus on fabric, interconnect, or network-on-chip verification at both IP and full-chip levels.
• Strong knowledge of SystemVerilog and UVM methodology.
• Hands-on experience with industry interconnect and bus protocols (e.g., AMBA AXI, CHI) and solid understanding of ordering, coherency, and flow-control semantics.
• Familiarity with SoC architectures, NoC topologies, and multi-initiator/multi-target interconnect designs.
• Proficiency in scripting languages such as Python, Perl, and TCL.

Nice-to-have

• Experience in performance verification and bandwidth/latency analysis for interconnect fabrics.
• Exposure to verification IPs for bus protocols or emulation platforms (e.g., Palladium, Veloce) for full-chip fabric validation.
• Experience with GPU or AI-accelerator SoC interconnect verification.
• Experience with formal verification or assertion-based verification (SVA) applied to fabric and protocol properties.

Education Requirements

B.S. or M.S. in Computer Engineering, Electrical Engineering, Computer Science, or a related technical field — or equivalent practical experience.

About the Company

Company: NVIDIA

Headquarters: Santa Clara, California, USA

NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.