Custom HBM Physical Design Engineer, Member of Technical Staff (MTS)

Job Title

Custom HBM Physical Design Engineer, Member of Technical Staff (MTS)

Role Summary

Hands-on physical design engineer in the Heterogeneous Integration Group responsible for implementing advanced HBM-capable SoC logic and base-die designs from netlist to GDSII. Works with RTL, verification, DFT, IP providers, packaging, and manufacturing to meet performance, power, area (PPA) and signoff requirements.

Experience Level

Senior-level. The posting indicates senior-level expectations and lists 15+ years as a preferred guideline.

Responsibilities

Primary responsibilities include implementation, closure, signoff, and cross-team integration for complex SoC designs.

• Own physical implementation for SoC blocks and/or top-level: floorplanning, placement, CTS, routing, and optimization to meet PPA targets.
• Drive timing closure across multi-mode/multi-corner (MMMC) scenarios; coordinate with RTL, architecture, and STA/signoff teams.
• Ensure correct clocking/reset strategy, power architecture, and SoC integration across teams.
• Integrate complex IP (controllers, microcontrollers, NOC, interfaces, MBIST/DFT logic, PHY-adjacent logic) with focus on timing and power integrity.
• Perform or coordinate physical signoff activities: DRC/LVS, IR drop/EM, timing signoff; resolve violations efficiently.
• Work with packaging, assembly, test, probe, and manufacturing to ensure manufacturability and quality.
• Support tapeout execution (checklists, ECO flows, signoff reviews) and post-silicon debug by correlating silicon behavior with PD/STA/power analysis.
• Identify flow gaps and improve productivity via scripting, automation, and methodology improvements.

Requirements

Must-have technical skills and experience for the role.

• Proven SoC physical design implementation experience from netlist to GDSII on advanced process nodes and complex designs.
• Proficiency with industry EDA tools (examples: Cadence Innovus/Tempus, Synopsys ICC2/PrimeTime, Siemens Calibre or equivalent).
• Experience with power intent and power delivery considerations (UPF/CPF concepts, power grid planning, power gating implications).
• Exposure to hierarchical physical design, top-level assembly, partitioning guidelines, and large-scale integration methodology.
• Knowledge of IR/EM analysis, noise, coupling/crosstalk and mitigation strategies.
• Demonstrated tapeout history on advanced foundries and familiarity with full-cycle SoC development flows.
• Strong scripting/automation skills (Python, TCL, Perl, and/or shell).

Nice-to-have:

• Experience with HBM or DRAM-adjacent SoC designs or memory-subsystem-heavy SoCs.
• Extensive prior experience (the posting lists 15+ years as preferred).

Education Requirements

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field (as stated in the posting).

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.