Custom CPU Physical Design Engineer (Lead/Staff/Senior Staff)
QualcommJob Title
Custom CPU Physical Design Engineer (Lead/Staff/Senior Staff)
Role Summary
Lead physical-design activities for custom CPU blocks and chip-level implementation, focusing on timing signoff, power distribution network (PDN), and meeting PPA (performance, power, area) targets. Work within a hardware engineering team contributing to RTL-to-GDSII implementation, static timing analysis (STA), and signoff flows.
Expect hands-on technical ownership of block or chip-level physical design tasks, collaborating with verification, implementation, and circuit teams to resolve timing, constraints, and manufacturability issues.
Experience Level
Senior - role targets experienced engineers (typical expectation: 7+ years in IC physical design). The posting also references 5–16 years range for similar roles.
Responsibilities
Key responsibilities include:
- Lead physical design and timing signoff for high-speed CPU cores and blocks.
- Perform STA, constraints validation, and timing closure to achieve PPA targets.
- Drive PDN methodology and analysis for chip/block implementation.
- Execute RTL-to-GDSII implementation, including floorplanning, placement, CTS, routing, and signoff checks.
- Collaborate with RTL, circuit, verification, and manufacturability teams to identify and fix time-critical paths and signal-integrity issues.
- Develop and maintain automation/scripts (Tcl/Perl) to support flows and flows integration.
- Lead a small engineering team on technical deliveries and resolve cross-functional issues.
Requirements
Must-have and preferred skills for the role.
- Must-have: Extensive experience in physical design and timing signoff for high-speed digital cores; strong STA knowledge and constraint handling.
- Must-have: Hands-on RTL-to-GDSII implementation experience and working knowledge of PDN design and analysis.
- Must-have: Proficiency with scripting for EDA flow automation (Tcl/Perl) and strong problem-solving skills.
- Must-have: Ability to work independently and lead technical deliveries with a small team; effective cross-functional collaboration.
- Nice-to-have: Experience with low-power flows (power gating, multi-Vt, supply management) and deep-submicron issues (leakage, signal integrity, DFM).
- Nice-to-have: Prior leadership of block- or chip-level PD, PPA convergence for high-frequency designs, and PDN methodology ownership.
Education Requirements
Bachelor's, Master's, or PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field. The posting lists degree-based alternatives including: Bachelor's + 2+ years, Master's + 1+ year, or PhD; some bullets reference candidates with 7+ years of IC design experience accompanying a Bachelors/Masters. Equivalent practical experience is not explicitly stated but industry experience expectations are emphasized.
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
