CPU Senior Floor Plan Engineer

Job Title

CPU Senior Floor Plan Engineer

Role Summary

Lead floorplanning and physical integration for CPU IP and full-chip assemblies, optimizing die size, aspect ratio, and package integration to meet performance, area, and manufacturability targets. Work with architects, physical-design cluster leads, clock and power teams, DFT, and packaging to deliver block-level floorplans and handoff-ready physical databases.

Experience Level

Senior engineer. Guidance: typically 4+ years post-Bachelor's or 3+ years post-Master's in a relevant field (see Education Requirements for details).

Responsibilities

Primary responsibilities include defining physical dimensions, integration, and driving early chip planning and convergence.

• Define CPU IP physical dimensions and die aspect ratios to optimize die-per-wafer and cost.
• Create and maintain physical databases for IP and hierarchical design handoffs.
• Integrate dies within a package and perform pre-tapeout checks.
• Collaborate with architects to place IP for latency and area trade-offs.
• Work with clock, power delivery, DFT, and logic teams to produce block-level floorplans for APR.
• Estimate die size, plan pin densities and boundaries to enable timing closure and routability.
• Evaluate and improve floorplan tools, methods and flows; identify and resolve partition/cluster and full-chip physical-design issues.
• Plan IO, global signal routing, clock and power distribution, and hard-IP integration.

Requirements

Must-have technical skills and relevant experience; preferred skills listed separately.

• Must-have:
  • Hands-on experience with floorplanning, APR flows, and physical-design verification flows using Synopsys or Cadence tools.
  • Proficiency in hierarchical/top-down design, budgeting, timing convergence, and physical convergence.
  • Strong knowledge of submicron process nodes and layout verification methodologies (LVS, DRC).
  • Experience handling IP/partition/block integration with multiple voltage and clock domains, ESD strategies, mixed-signal blocks, and advanced package technologies.
• Nice-to-have:
  • Scripting experience for automation (Tcl, Perl, or Python).
  • Experience in feature feasibility studies and advanced design flow methodologies.
  • Proven ability to collaborate across functions and geographies.

Education Requirements

Minimum: Bachelor's degree in Electrical Engineering, Electronics Engineering, or equivalent with 4+ years of hands-on experience; or Master's degree in a relevant field with 3+ years of hands-on experience. The posting also allows equivalent education or practical experience in related technical fields.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.