CPU Senior Floor Plan Engineer

Job Title

CPU Senior Floor Plan Engineer

Role Summary

Responsible for defining physical dimensions and floorplanning of CPU IP to optimize die size, yield, and package integration. Works with architecture, physical design, clock, power delivery, and packaging teams to produce block-level floorplans, integration checks, and collateral required for automatic place-and-route (APR) and tape-out.

Role is part of Intel's CPU design team and follows a hybrid work model (split on-site and off-site at the assigned Intel site).

Experience Level

Senior. Minimum experience guidance from the posting: typically 3+ years hands-on experience with a Bachelor's degree, or 2+ years with a Master's degree.

Responsibilities

Primary responsibilities include planning and executing floorplan and IP integration tasks across chip and package levels.

• Define physical dimensions of CPU IP and optimize die size and die-per-wafer metrics.
• Perform full-chip and package integration, including pre-tape-out checks and database creation for the IP.
• Collaborate with architects to optimize IP placement for latency and area/aspect ratio trade-offs.
• Create specifications and collaterals for block-level floorplanning and APR flows.
• Work with clock, logic, and power teams on block-level floorplans, clock/power distribution, and metal allocation trade-offs.
• Estimate die size, evaluate floorplan tools and flows, and plan pin densities for routability and timing closure.
• Identify and resolve design issues at partition/cluster and full-chip levels; integrate hard IP and multi-voltage/multi-clock domains.

Requirements

Must-have technical skills and experience; preferred items stated separately.

• Proven expertise with floorplanning, APR flows, and physical design verification flows using Synopsys or Cadence toolsets.
• Experience with hierarchical/top-down physical design methodology, budgeting, timing convergence, and physical closure.
• Strong knowledge of submicron process nodes and layout verification methodologies (LVS, DRC).
• Experience integrating IP/partitions/blocks with multiple voltage and clock domains, ESD strategies, mixed-signal blocks, and advanced package technologies.
• Ability to estimate die size and assess floorplan tool/method trade-offs for manufacturability and cost.
• Nice-to-have: scripting for automation (Tcl, Perl, Python); experience in distributed/cross-geography teams; familiarity with feature feasibility and advanced design flows.

Education Requirements

Minimum: Bachelor's degree in Electrical Engineering, Electronics Engineering, or equivalent field. Alternate: Master's degree in a relevant field (with lower experience requirement). The posting allows equivalent education or equivalent practical experience as a substitute for degree requirements.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.