CPU Physical Design Timing Engineer

Job Title

CPU Physical Design Timing Engineer

Role Summary

Work on CPU timing closure for Oryon CPU cores within Qualcomm's CPU Engineering team. Drive STA setup, timing analysis, debug and signoff across multiple PVT corners and voltage domains to meet performance, power and area goals.

Collaborate with microarchitecture, RTL and central timing methodology teams; develop automation and STA infrastructure used across CPU projects and advanced process nodes (N2/N3).

Experience Level

Mid-level (typically 2+ years hardware/engineering experience; role expects practical STA and back-end implementation experience).

Responsibilities

Primary responsibilities include static timing analysis, convergence and automation to achieve timing signoff for CPU cores.

• Setup, convergence, review and signoff of STA for multi-mode, multi-voltage domain CPU designs.
• Perform timing analysis, validation and debug across PVT corners using PrimeTime and/or Tempus.
• Run STA flows and optimize them; perform Spice-to-STA correlation and troubleshoot miscorrelations at different design levels and modes.
• Develop and maintain scripts and utilities to enable CPU STA signoff flows and timing infrastructure.
• Evaluate timing methodologies and tools across designs and technology nodes; propose and implement solutions for timing issues.
• Work with RTL and implementation teams on clock tree synthesis, latch transparency, multi-cycle/0-cycle path handling, and closure strategies.
• Document findings and communicate timing status and risks to cross-functional teams.

Requirements

Must-have technical skills and experience; preferred items listed separately.

• Strong automation skills using TCL, Perl or Python for STA and flow scripting.
• Experience developing automation for STA signoff flows and timing methodology.
• Hands-on experience with STA tools such as PrimeTime and/or Tempus.
• Practical experience debugging timing issues, root-cause analysis and proposing fixes.
• Familiarity with digital back-end implementation flows and tools (ICC/ICC2, Innovus) and RTL-to-GDS flows.
• Knowledge of CTS, timing constraints management, latch transparency, and multi-cycle path handling.
• Strong technical writing and cross-team communication skills.

Nice-to-have:

• Experience driving timing convergence at chip and hard-macro levels.
• Familiarity with crosstalk, signal integrity, layout parasitic extraction and feed-through handling.
• Basic understanding of device physics.
• History of framework, tool or utility development for EDA flows.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 2+ years of relevant engineering experience; OR Master's in those fields with 1+ year of relevant experience; OR PhD in a related technical field. (Degree or equivalent practical experience as described in minimum qualifications.)

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.