CPU Physical Design Timing Engineer
QualcommJob Title
CPU Physical Design Timing Engineer
Role Summary
Work on timing closure for Oryon CPU cores within Qualcomm's CPU engineering team. The role focuses on developing timing constraints, STA signoff flows, and automation that support multi-mode, multi-voltage CPU implementations targeting advanced process nodes.
Collaborate with microarchitecture, RTL, implementation and central timing methodology teams to meet power, performance and area (PPA) goals.
Experience Level
Level - Mid-Career. Expect mid-level candidates with several years of industry experience (typical range ~5–7 years); exact minimums vary by degree (see Education Requirements).
Responsibilities
Key responsibilities include STA setup and closure, timing analysis and tooling, and automation to support CPU signoff.
- Set up, converge, review and sign off STA for multi-mode, multi-voltage CPU core designs.
- Perform timing analysis, validation and debugging across multiple PVT corners using PrimeTime and/or Tempus.
- Develop and optimize STA signoff flows and run spice-to-STA correlation.
- Diagnose root causes of timing miscorrelation across design levels and propose solutions.
- Evaluate timing methodologies and tools across designs and technology nodes.
- Produce technical documentation and communicate findings across cross-functional teams.
Requirements
Must-have technical skills and experience; preferred items are listed separately.
- Strong automation and scripting skills (TCL, Perl, Python) for STA flow and tool integration.
- Practical experience with static timing analysis tools and flows (PrimeTime, Tempus).
- Hands-on experience with timing signoff, constraint development, and closure methodologies (CTS, multi-cycle, 0-cycle handling, latch transparency).
- Familiarity with digital back-end implementation flows (ICC, Innovus) and RTL-to-GDS flows.
- Ability to debug timing issues at block and chip levels and work across microarchitecture and implementation teams.
- Good technical writing and cross-team communication skills.
Nice-to-have:
- Experience with spice correlation, crosstalk/noise and signal integrity, parasitic extraction handling.
- Experience driving timing convergence for chip-level and hard-macro designs and on leading-edge nodes (N2/N3).
- Background in device physics or deeper ASIC back-end methodologies.
Education Requirements
Required: Bachelor's, Master’s, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. Minimum experience varies by degree: typical minimums listed in the posting were roughly Bachelor's +6+ years, Master’s +5+ years, PhD +4+ years.
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
