CPU Physical Design Engineer

Job Title

CPU Physical Design Engineer

Role Summary

Design and implement physical layouts for CPU ASICs, delivering place-and-route, timing closure, power-intent implementation, and clock tree design for high-speed processors. Collaborate with verification, architecture, CAD, and bring-up teams to meet performance, power, and area targets and support silicon bring-up and debugging.

Experience Level

Mid-level. Typical candidates have multiple years of ASIC physical design experience; the team considers a broad range of experience from early mid-career to senior engineers.

Responsibilities

Key responsibilities include:

• Execute place-and-route implementation for CPU designs using industry P&R tools.
• Perform static timing analysis and lead timing closure efforts.
• Implement and verify power intent for multiple power domains (UPF/CPF).
• Design and optimize clock trees for high-speed CPU operation.
• Create and validate constraints; manage constraint flows and related tools.
• Run formal checks and CAD signoff flows as part of tapeout readiness.
• Develop scripts and automation to improve flow efficiency and quality.
• Collaborate with microarchitecture, verification, and bring-up teams to debug silicon and resolve physical-design issues.

Requirements

Must-have technical skills, tools, and experience:

• Extensive place-and-route experience with Synopsys Fusion Compiler or Cadence Innovus.
• Hands-on experience across the complete ASIC flow with focus on power/performance/area optimization.
• Static timing analysis using Synopsys PrimeTime and/or Cadence Tempus.
• Constraint generation and validation; familiarity with constraint management tools.
• Power-intent implementation for complex multi-domain designs (UPF/CPF).
• Formal verification experience (Mentor Formality or Cadence Conformal).
• Scripting and programming: Perl, Tcl, Python; C++ experience desirable.
• Experience with CPU micro-architecture, critical path analysis, low-power techniques, and high-speed CPU implementation.
• Clock tree implementation techniques for high-speed designs and Verilog coding exposure.
• Strong ASIC development, problem solving, and silicon-debugging skills.

Education Requirements

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field is required. A Master’s degree in Electrical/Electronics Engineering or a related field with 2+ years of hardware engineering experience is mentioned as an advanced qualification. Equivalent practical experience may be considered.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.