CPU Physical Design Engineer

Job Title

CPU Physical Design Engineer

Role Summary

Responsible for block- and chip-level physical implementation and timing signoff of high-speed CPU cores. Works within Hardware/ASIC engineering teams to deliver RTL-to-GDSII implementation, signoff-quality STA, and power-delivery network (PDN) solutions.

The role involves leading technical deliveries for complex IC designs, driving convergence for performance/power/area targets, and collaborating with verification, circuit, and RTL teams to resolve physical-design issues.

Experience Level

Senior — typically 7+ years of relevant IC physical design experience; the posting references experience ranges of 7–14 years for similar roles.

Responsibilities

Key responsibilities include:

• Lead block- or chip-level physical design, placement, routing and timing closure for high-speed CPU cores.
• Perform static timing analysis (STA) and timing signoff to meet PPA targets.
• Define and validate PDN methodology and power-delivery solutions.
• Implement low-power techniques (power gating, multi-Vt flows, supply management).
• Execute RTL-to-GDSII implementation flow and coordinate with verification teams for constraints and signoff.
• Analyze circuit-level critical paths and address deep-submicron issues (leakage, signal integrity, DFM).
• Develop and maintain automation/scripting (Tcl/Perl) to support design flows.
• Mentor/coordinate small teams to deliver technical milestones.

Requirements

Must-have skills and experience:

• 7+ years experience in physical design and timing signoff for high-speed cores.
• Proven experience driving high-frequency design convergence to meet PPA targets.
• Hands-on experience with STA and signoff flows at block and chip level.
• Strong understanding of PDN methodology and power-delivery validation.
• Familiarity with low-power implementation techniques and multi-voltage flows.
• Ability to reason at the circuit level about timing-critical paths and deep-submicron effects.
• Practical scripting skills (Tcl/Perl) to automate physical design tasks.
• Strong problem-solving and independent execution skills; able to lead small engineering teams.

Nice-to-have:

• Experience with large CPU core implementations and chip-level closure.
• Prior leadership of STA/PDN teams or ownership of cross-functional signoff activities.

Education Requirements

Bachelor's, Master’s or PhD in Computer Science, Electrical/Electronics Engineering, or a related engineering field. The posting lists degree+experience combinations (e.g., Bachelors + 4+ years, Masters + 3+ years, PhD + 2+ years) and also references Masters/Bachelors with 7+ years for this level. Equivalent practical experience in IC/physical design is implicitly considered via the degree-plus-experience options.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.