CPU/NPU Architecture RTL Design Engineer (Sr level and up)

Job Title

CPU/NPU Architecture RTL Design Engineer (Sr level and up)

Role Summary

Design and deliver RTL for CPU and NPU blocks used in Qualcomm's Snapdragon processors and Hexagon NPU. Work on micro-architecture, RTL implementation, and optimizations for performance, power, and area within the Hexagon NPU team in Markham, Ontario.

Role involves collaborating with architecture, verification, and integration teams to produce high-performance, energy-efficient processor IP for on-device AI and general-purpose CPU workloads.

Experience Level

Senior-level (Sr and up). The posting indicates an ideal candidate with 5+ years of relevant experience; minimum experience requirements vary by degree (see Education Requirements).

Responsibilities

The engineer will develop RTL and micro-architecture for CPU/AI processors and support design integration and debug.

• Architect and implement RTL for CPU and NPU blocks (including control and datapath).
• Write and review RTL code, synthesize and iterate to meet timing, power, and area targets.
• Collaborate with verification, validation, and integration teams to bring IP into SoC.
• Perform micro-architecture design for instruction fetch, scheduling, renaming, and out-of-order pipelines.
• Design and optimize memory subsystems: load/store, caches, atomics, coherence and consistency.
• Implement and optimize compute units (fixed/floating-point units, matrix multiply, vector extensions).
• Analyze and improve PPA (power, performance, area); work with physical design and power teams.
• Support debug architecture and system-level debug during bring-up and integration.

Requirements

Key technical skills and domain experience required for successful performance in this role.

• Must-have: Significant RTL design and RTL coding experience for high-performance CPU or AI processors.
• Must-have: Strong knowledge of CPU/AI processor micro-architecture and architecture (instruction fetch, scheduling, renaming, dispatch, schedulers).
• Must-have: Experience with memory subsystems, load/store units, caches, coherence, and atomics.
• Must-have: Experience optimizing PPA; familiarity with synthesis and timing closure trade-offs.
• Must-have: Debugging complex RTL and system integration issues.
• Nice-to-have: Computer arithmetic expertise, fixed-point and floating-point design.
• Nice-to-have: Experience with matrix multiply engines, vector extensions, branch prediction, out-of-order execution, multi-threaded/multi-processor designs.
• Nice-to-have: Experience with RISC-V and familiarity with ASIC design, verification, validation, and integration flows.

Education Requirements

Bachelor's degree in Science, Engineering, or a related field plus 2+ years of ASIC design/verification/validation/integration experience; OR Master's degree in Science, Engineering, or a related field plus 1+ year of relevant experience; OR PhD in Science, Engineering, or a related field. (The posting lists these degree-based minimums explicitly.)

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.