CPU IP Design & Verification Engineer - RISC-V (New College Graduate, 2027)

Job Title

CPU IP Design & Verification Engineer - RISC-V (New College Graduate, 2027)

Role Summary

Join the MIPS CPU IP Engineering team to develop and verify advanced RISC-V processor IP. The role involves CPU microarchitecture, SystemVerilog RTL implementation, functional verification, power/performance/area analysis, automation, and debug. Positions available in Austin, TX or Santa Clara, CA.

Experience Level

Entry-level - new college graduate (intended for candidates graduating in 2027; typically 0–2 years of experience).

Responsibilities

Deliver design and verification work for CPU IP and collaborate with cross-functional teams. Key responsibilities include:

• Design and implement RISC-V CPU microarchitecture and SystemVerilog RTL.
• Contribute to instruction fetch/decode, execution, load/store, caches, memory interfaces, control/status registers, exceptions, and interrupts.
• Develop verification tests, assertions, checkers, and functional coverage.
• Run simulations and regressions; debug failures using logs, architectural traces, and waveforms.
• Support functional and coverage closure through design and verification reviews.
• Perform CPU power, performance, and area analysis and optimization.
• Develop automation and scripting (Python, C/C++, or similar) to improve design, verification, regression, and debug productivity.
• Collaborate with architecture, design, verification, performance, and implementation teams to deliver CPU IP.
• Perform duties in a safe and compliant manner and support Environmental, Health, Safety & Security programs.

Requirements

Must-have technical skills and attributes:

• Fluent in English (written and verbal).
• Strong foundation in digital logic design and computer architecture.
• Hands-on experience with Verilog or SystemVerilog via coursework, research, internship, or projects.
• Understanding of CPU fundamentals: pipelines, instruction execution, loads/stores, caches, and memory hierarchy.
• Programming or scripting experience (Python, C/C++, or similar).
• Strong analytical, problem-solving, and debugging skills.

Nice-to-have:

• Prior internship or co-op experience in related roles.
• Knowledge of the RISC-V ISA.
• Experience with SystemVerilog/UVM, assertions, functional coverage, or constrained-random verification.
• CPU architecture, microarchitecture, FPGA, ASIC, or processor-design project experience.
• Experience with simulation, waveform debug, Git, and Linux.
• Exposure to synthesis, lint, clock-domain crossing analysis, formal verification, or timing analysis.
• Assembly-language programming experience.
• Interest in AI-assisted engineering tools for RTL design, verification, automation, and debug.

Education Requirements

Graduating with a Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field from an accredited program. Applicants must have an overall GPA of at least 3.0.

About the Company

Company: GlobalFoundries

Headquarters: Saratoga Springs, New York, USA

GlobalFoundries is a leading contract manufacturer for the global semiconductor industry, with facilities in multiple countries, including the USA. The company develops a broad portfolio of semiconductor technologies and employs around 13,000 people worldwide. GlobalFoundries focuses on enhancing competitiveness in specialized application solutions and fostering innovation in mobile communications, consumer electronics, and automotive applications.