CPU Floorplan Lead

Job Title

CPU Floorplan Lead

Role Summary

Lead floorplanning and pin-placement for CPU IP and SoC integration to optimize die size, manufacturability, and performance. Work across architecture, physical design, clock/power delivery, DFT and packaging to define chip layout, create physical databases, and complete checks prior to tapeout.

Experience Level

Senior-level role. Posting indicates 10+ years of industry experience; minimum 4 years specifically in floorplanning.

Responsibilities

Key responsibilities focus on chip planning, physical integration, and collaboration across teams to ensure timing, routability, and manufacturability.

• Define physical dimensions and aspect ratios for CPU IP and overall chip to optimize die size and yield.
• Drive die-level integration, create and maintain physical databases, and perform tapeout readiness checks.
• Collaborate with architects to place IPs for latency and area trade-offs across SKUs.
• Work with clock, logic, and power teams to deliver block-level floorplans for APR and make metal allocation tradeoffs.
• Engage with DFT, package, and physical design leads to plan pin densities, I/O, and partition boundaries for timing closure and routability.
• Estimate die size, evaluate floorplanning tools and flows, and identify/resolve design issues at cluster and full-chip levels.

Requirements

Must-have technical skills and experience required for the role. Preference items are noted where applicable.

• Extensive ASIC physical design experience, including floorplanning, placement and routing flows, and physical design verification.
• Minimum 4 years hands-on floorplanning experience; demonstrated experience across full-chip and hierarchical flows.
• Expert user of floorplanning tools (examples cited: ICC2 DP or Cadence Encounter) and familiarity with P&R flows and related CAD tools.
• Strong knowledge of clock and power distribution, global signal planning, I/O planning, and hard IP integration.
• Experience addressing SoC issues: multiple voltage/clock domains, ESD strategies, mixed-signal integration, and advanced packaging.
• Understanding of design-for-yield and manufacturability considerations and physical convergence for timing and routability.
• Good communication and cross-team collaboration skills to coordinate with architecture, DFT, package, and manufacturing teams.

Education Requirements

Requires a B.Tech or M.Tech in Electrical/Electronics Engineering. Preference for a Master’s with VLSI/microelectronics specialization. The posting specifies 10+ years of overall experience (senior level) and at least 4 years in floorplanning.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.