CPU Floorplan Lead

Job Title

CPU Floorplan Lead

Role Summary

Lead floorplanning and physical integration for CPU IP and SoC partitions, driving die-size optimization, package-level die integration, and physical database creation to prepare designs for tapeout.

Work with architecture, clock, logic, power delivery, package and physical-design teams to produce floorplans, pin placement, and collateral for automatic place-and-route (APR) and verification flows.

Experience Level

Senior-level individual contributor. Role specifies senior experience (10+ years total experience as listed in the position requirements).

Responsibilities

Accountabilities include defining physical boundaries, integration checks, and producing deliverables for downstream APR and verification.

• Define IP physical dimensions and die planning to optimize die size, yield and cost.
• Create and maintain physical databases and floorplan collateral for IP blocks and higher hierarchies.
• Perform package-level die integration and pre-tapeout checks.
• Collaborate with architects to optimize placement for latency and area/aspect ratio tradeoffs.
• Work with clock, logic and power teams to deliver block-level floorplans suitable for APR.
• Coordinate I/O planning, pin placement and pin density planning to support timing closure and routability.
• Estimate die size, evaluate floorplanning tools, methods and flows, and drive improvements.
• Identify and resolve physical-design issues across partitions and full-chip integration.

Requirements

Must-have technical skills and domain experience for effective floorplanning and integration.

• Expertise in floorplanning, clock and power distribution, global signal planning, I/O planning, and hard-IP integration.
• Proven experience with ASIC/SoC physical-design flows including APR and physical-design verification.
• Hands-on use of floorplanning tools such as ICC2 DP or Cadence Encounter (expert user level expected).
• Experience integrating mixed-voltage/clock domains, mixed-signal blocks, and advanced package technologies.
• Familiarity with design-for-yield and manufacturability issues and ESD strategies.
• Comfortable with hierarchical/top-down design approaches, budgeting and physical/timing convergence.

Education Requirements

Required: B.Tech. or M.Tech. in Electrical/Electronics Engineering. The posting prefers a Master’s degree with VLSI/microelectronics specialization. The role lists senior experience expectations (10+ years total experience) and notes a minimum of ~4 years specifically in floorplanning.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.