CPU Core Design Verification Testbench Lead

Job Title

CPU Core Design Verification Testbench Lead

Role Summary

Lead development and ownership of CPU core-level verification testbenches for high-performance out-of-order RISC-V cores. You will design and evolve testbench infrastructure, drive functional verification, and coordinate verification across simulation, emulation, and post-silicon environments.

This is a hybrid role based out of Austin, TX or Santa Clara, CA.

Experience Level

Senior — typically requires 8+ years of experience in CPU verification, CPU testbench development, or closely related digital design work.

Responsibilities

Deliver hands-on testbench and verification capabilities that validate CPU core features, ISA behavior, and microarchitectural scenarios.

• Lead hands-on development and ownership of CPU core-level testbenches for out-of-order RISC-V cores.
• Own and evolve CVM-based verification methodology and reusable testbench components.
• Plan and execute functional verification campaigns for core features, ISA extensions, and microarchitectural edge cases.
• Implement UVM environments and create assembly, C/C++, and C++ functional models for cores and un-core components (e.g., APIC, IOMMU).
• Debug regressions, close coverage gaps, and improve testbenches across simulation, emulation, and post-silicon flows.
• Develop Python-based orchestration and tooling that integrates AI-assisted agents to accelerate triage and root-cause analysis across logs, waveforms, and DBs.
• Collaborate with RTL designers, DV engineers, emulation, and post-silicon teams to resolve issues and improve verification effectiveness.

Requirements

Must-have skills and experience to perform the role; nice-to-have items listed separately.

• Must-have: 8+ years in CPU verification, CPU testbench development, or closely related digital design roles.
• Must-have: Proven experience building and owning CPU core-level testbenches (not only using existing environments).
• Must-have: Deep understanding of high-performance out-of-order CPU microarchitecture and ISA behavior.
• Must-have: Experience with CVM verification methodology; strong experience with UVM is a significant plus.
• Must-have: Hands-on with RTL, waveform/log analysis, regression debug, and cross-functional troubleshooting across simulation, emulation, and silicon.
• Must-have: Proficiency developing stimulus and models in assembly, C/C++, and C++ functional modeling.
• Must-have: Experience building automation and orchestration tooling (Python) and applying AI-assisted verification workflows for debug, stimulus generation, or coverage analysis.
• Nice-to-have: Prior work on RISC-V cores, APIC/IOMMU, or large multi-core clusters; prior leadership of DV teams or mentoring experience.

Education Requirements

Not specified.

About the Company

Company: Tenstorrent

Headquarters: Austin, Texas, United States

Tenstorrent is a technology company focused on designing innovative computing solutions. They are known for their expertise in the development of advanced hardware, including ASICs and SoCs, aimed at enhancing performance and efficiency in various applications.