CPU Clock Design Engineer

Job Title

CPU Clock Design Engineer

Role Summary

The CPU Clock Design Engineer designs, implements, analyzes, and optimizes clock distribution networks and related circuitry for high-performance CPU and SoC products. This role works with architecture, design, physical implementation, validation, and EDA teams to achieve timing closure, power and performance targets, and scalable clocking solutions.

This position is eligible for a hybrid work model and is based primarily in Austin, TX (additional location: Hillsboro, OR).

Experience Level

Mid-level. Typical requirements: Bachelor's in a relevant STEM field with 3+ years of experience, or a Master's with 1+ years of experience; experience should cover several core competency areas listed below.

Responsibilities

Primary responsibilities include design and verification of clocking solutions across the product lifecycle.

• Design, implement, and optimize clock distribution networks for CPU and SoC products.
• Develop clock architecture and clock tree synthesis (CTS) methodologies.
• Perform static timing analysis (STA) and support timing closure for complex designs.
• Create custom circuits and library cells for clock networks.
• Analyze PPA (performance, power, area) and timing tradeoffs; drive optimizations.
• Develop automation and productivity scripts using languages such as Python, Perl, TCL, or Shell.
• Collaborate with architecture, physical implementation, validation, and EDA teams to resolve technical issues.
• Support debug, validation, and optimization activities through the product development lifecycle.
• Influence future methodologies, flows, and clocking technologies.

Requirements

Must-have technical skills and experience; preferred items are listed separately.

• Hands-on experience in digital circuit design and VLSI design.
• Experience in physical design and clock tree synthesis (CTS).
• Proven experience with static timing analysis (STA) and timing closure methodologies.
• Experience in logic design and custom circuit design for clocking networks.
• Knowledge of semiconductor design methodologies and full-chip design flows.
• Proficiency in one or more scripting/programming languages (Python, Perl, TCL, Shell, or similar) for automation.
• Ability to analyze performance, power, area, and timing tradeoffs and drive technical issues to closure.

Nice-to-have:

• Hands-on experience in high-frequency custom clock network design on advanced technology nodes.
• Experience with PLL/DLL architecture and design.
• Expertise in timing constraint adaptation and advanced timing closure techniques.
• Deep familiarity with full-chip EDA tools and flows.

Education Requirements

Bachelor's degree in Electrical/Computer Engineering, Computer Science, or a related STEM field (with 3+ years of relevant experience), or a Master's in the same fields (with 1+ years of educational or work experience). PhD in Electrical/Computer Engineering or a related field is listed as preferred. The role also considers relevant industry experience, internships, coursework, or research as qualifying background.

Benefits information: Intel Benefits

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.