Constraints Verification Applications Engineer
SynopsysJob Title
Constraints Verification Applications Engineer
Role Summary
Customer-facing application engineer responsible for solving constraint (SDC) generation, verification, management, and signoff challenges across the RTL-to-signoff flow. Work with semiconductor design teams, Synopsys R&D, and account teams to deploy and improve constraint verification methodologies and tools.
Experience Level
Mid-level - typically requires 5+ years of hands-on industry experience in ASIC design or verification.
Responsibilities
Primary responsibilities include technical customer engagement, tool deployment, debugging, and methodology development.
- Partner with semiconductor customers to resolve end-to-end constraint flow issues at RTL and netlist levels.
- Deploy and optimize constraint verification and signoff tools across customer flows.
- Analyze and debug MCP, false path, generated-clock issues and trace problems through synthesis and timing signoff.
- Collaborate with R&D and product validation to develop methodologies and feed product requirements back into roadmaps.
- Develop and maintain automation scripts to streamline constraint generation, verification, and management workflows.
- Coordinate with account teams to drive tool adoption and support project delivery.
- Gather and track flow requirements based on customer feedback and engineering judgment, including multi-modal analysis and equivalence checks.
Requirements
Must-have technical skills and experience for successful performance in this role.
- End-to-end experience with SDC and constraint flows: generation, verification, management, and signoff.
- Deep knowledge of constraint methodologies: multi-cycle paths, false paths, generated clocks, multi-modal analysis, and equivalence checks at RTL and netlist levels.
- Proven experience with constraint verification and signoff tools (for example, Fishtail/TCM, SpyGlass-Constraints, PrimeTime or equivalents).
- Strong RTL knowledge (VHDL, Verilog, SystemVerilog) and solid understanding of ASIC design flows from RTL to tapeout.
- Experience with static timing analysis (STA), timing closure processes, and constraint report analysis/debugging.
- Advanced scripting skills for automation and flow development (TCL, Unix shell, Perl, or Python).
Education Requirements
BE/BTech or ME/MTech in Electronics Engineering, Computer Science, or Microelectronics. The posting specifies 5+ years of industry experience in ASIC design or verification.
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
