Collateral Design and DFM Engineer

Job Title

Collateral Design and DFM Engineer

Role Summary

Lead development and enhancement of Design-for-Manufacturability (DFM) methodologies to improve yield, performance, and ramp for advanced logic foundry technologies. Work at the intersection of technology development and high-volume manufacturing to translate silicon learning into design and process improvements.

Experience Level

Senior — role expects experienced engineers; minimum guidance from posting indicates 10+ years of relevant DTCO/DFM experience.

Responsibilities

Primary responsibilities focus on defining DFM rules, collaborating across functions, and improving inline yield detection and optimization.

• Lead cross-functional teams (process integration, device, yield, design, OPC/RET/DR, DTP/CAD) to define and enhance DFM and design rules for advanced logic technologies.
• Translate silicon yield learning into layout, DTCO, and flow updates for earlier detection of issues during design.
• Develop and refine yield tools and flows to support inline yield detection, analysis, and optimization.
• Predict and develop rules to avoid layout and design marginalities by understanding process flows and manufacturing constraints.
• Support scribe-line layout design and process monitoring structure development for test chips and production ramps.

Requirements

Key technical and professional requirements. Education specifics are listed under Education Requirements below.

• 10+ years of hands-on experience in DTCO and/or DFM within a semiconductor foundry or advanced technology development environment.
• Strong understanding of DTCO topics including SRAM, standard cells, process integration, yield, and device behavior.
• Proven experience leading cross-functional groups to define derivative architectures, design rules, transistors, and interconnects.
• Experience in scribe-line layout design and process monitoring structure development.
• Proven track record implementing DFM solutions in a foundry environment across multiple customer requirements and market segments.

• Coding/scripting skills for tool/flow development.
• Hands-on experience with advanced node test chip design and scribe-line optimization (3nm–16nm FinFETs and sub-3nm GAA FETs), including backside power delivery.
• Familiarity with physical design flows for yield analysis, DRC, and verification; proficiency in design rule development, validation, and waiver management.
• Experience with foundry customer design flows and manufacturing constraints across application domains.

Education Requirements

Minimum stated: Master's or Ph.D. in Electrical Engineering, Physics, or a related field. The posting pairs these degrees with a 10+ year experience expectation. "Related field" and advanced-technology/foundry experience are indicated; no explicit mention of acceptable equivalent practical-experience language beyond the degree requirement.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.