Chiplet Physical Design Engineer

Job Title

Chiplet Physical Design Engineer

Role Summary

Join a team designing and integrating multiple chiplets into System-in-Package (SiP) solutions for high-performance CPU and AI silicon. The role owns synthesis and place-and-route for high-speed CPU core designs and drives timing, power, and area outcomes on advanced process nodes.

Work closely with internal teams across the United States, Japan, and other global sites, and with external partners to deliver manufacturable, high-performance silicon.

Experience Level

Senior — the posting expects experienced candidates; hiring targets engineers with 10+ years of relevant industry experience in physical design.

Responsibilities

Primary responsibilities include ownership of physical implementation tasks and cross-team coordination for multi-chiplet SiP projects.

• Lead synthesis and place-and-route (P&R) flows for CPU core blocks and chip-level integration.
• Drive timing closure, ECO flows, and parasitic/voltage (PV) convergence at block and chip level.
• Optimize designs for performance, power, and area on advanced process nodes (multi-GHz designs, 3nm and below).
• Collaborate with architects, frontend designers, verification, packaging, and external partners to integrate chiplets into SiP systems.
• Develop and improve physical design methodology and automation to scale across projects.
• Mentor and review work of other engineers; provide technical guidance on closure strategy.
• Participate in design reviews, schedule planning, and risk mitigation for tapeout readiness.

Requirements

Candidates must demonstrate strong hands-on physical design skills and the ability to deliver in complex, multi-stakeholder programs.

• 10+ years industry experience in physical design for CPU or GPU products.
• Proven hands-on experience with Synopsys and/or Cadence toolflows across synthesis, P&R, and design closure.
• Expertise in timing closure, ECO flows, and PV convergence at both block and chip level.
• Required scripting skills: TCL required; Python or similar strongly preferred.
• Comfortable working on advanced process nodes and multi-GHz designs (practical experience at 3nm or below preferred).
• Strong English communication skills and ability to collaborate across distributed global teams.
• Eligibility to access U.S. export-controlled technology (citizenship/permanent residency or ability to obtain required government license) may be required for employment.

• Experience with chiplet/SiP integration and multi-die packaging considerations.
• Background in CPU or RISC-V microarchitecture implementation and verification flow interactions.
• Experience standardizing and scaling physical design methodologies across projects.

Education Requirements

Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or Computer Science.

About the Company

Company: Tenstorrent

Headquarters: Austin, Texas, United States

Tenstorrent is a technology company focused on designing innovative computing solutions. They are known for their expertise in the development of advanced hardware, including ASICs and SoCs, aimed at enhancing performance and efficiency in various applications.