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Chip-Level Defect Localization and Failure Analysis Engineer - RDSS Intern

NVIDIA
November 2, 2026
Internship
On-site
Hsinchu, Taiwan
Test Engineering Jobs, Level - Entry or Early Career

Job Title

Chip-Level Defect Localization and Failure Analysis Engineer - RDSS Intern

Role Summary

Internship position in electro-optical electrical failure analysis (EFA) within the RDSS electro-optical FA team in Hsinchu. The role performs chip-level defect localization and analysis to support product development, yield ramp, reliability, and customer-return investigations for advanced flip-chip CMOS devices.

Experience Level

Entry-level internship (RDSS program).

Responsibilities

Core hands-on and analytical tasks the intern will perform:

  • Perform electro-optical failure analysis: photon emission, laser-voltage-probing, and soft-defect-localization (SDL/LADA) to locate defects on advanced flip-chip devices.
  • Analyze production test results (error logs, flop mapping, software diagnosis) and narrow failing logical areas to identify failing transistors or cells.
  • Set up test loops on Advantest 93k tester software for design-debug and failure verification.
  • Use CAD layout tools for in-chip navigation and logic circuit simulation tools to support localization and root-cause analysis.
  • Work in Unix environments for CAD, simulation, and tester software integration.
  • Collaborate with cross-functional teams (DFT, test, product engineers, physical FA groups) and present findings to guide physical root-cause analysis and foundry process improvements.
  • Support die-probe and package second-source activities for FA readiness.

Requirements

Minimum technical skills and experience expected for successful performance in the role.

  • Basic understanding of design-for-test (DFT) for large-scale logical testing, including scan-chain based structural and at-speed testing and fundamentals of test compression.
  • Hands-on lab experience setting up and debugging test environments and test bring-up in the Advantest 93k environment.
  • Functional knowledge of transistor device physics and advanced CMOS manufacturing processes.
  • Experience with CAD layout tools and logic circuit simulation tools.
  • Basic Unix skills for running CAD, simulation, and tester software.
  • Strong written and verbal communication skills for cross-team collaboration and presenting analysis results.
  • Nice-to-have: familiarity with PFA tools/techniques (SEM, TEM, FIB, AFM) and scripting/programming languages such as PERL, TCL, C++.

Education Requirements

Master's or PhD in Electrical Engineering, Computer Engineering, or a closely related technical field. Applicants should confirm eligibility for the 2027 RDSS program with the local district office before applying.


About the Company

Company: NVIDIA

Headquarters: Santa Clara, California, USA

NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.

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Date Posted: 2026-10-29