Chip Lead / Physical Design Director
Cadence Design SystemsJob Title
Chip Lead / Physical Design Director
Role Summary
Lead a Physical Design team within the Cadence Performance Solutions Group to deliver RTL-to-GDS services for advanced FinFET nodes. Act as the technical owner for complex SoC projects, working directly with customers to meet Performance, Power, Area and Schedule (PPAS) targets.
Collaborate with internal teams and tools R&D to improve methodologies, automate flows, and ensure successful design closure for markets such as data center, automotive, and AI.
Experience Level
Senior — requires fifteen or more years of industry experience in Physical Design.
Responsibilities
Primary responsibilities include technical leadership, customer engagement, and cross-functional coordination to achieve design closure and PPA targets.
- Lead Physical Design and DFT teams on SoC projects from RTL/Netlist to GDS delivery.
- Own technical decisions, design trade-offs, and problem solving to meet PPA and schedule requirements.
- Advise customers on foundry/node selection, libraries, and memory compiler choices; define sign-off criteria.
- Coordinate with RTL/synthesis teams to ensure metrics are met before physical design phase gates.
- Partner with Cadence R&D teams to improve tools, flows, and AI-driven automation.
- Document and share best practices and lessons learned to improve efficiency and success rates.
Requirements
Must-have technical skills, experience, and behaviors.
- Fifteen or more years of industry experience in Physical Design.
- Strong knowledge of digital design fundamentals, semiconductor fundamentals, and static timing analysis (including timing constraints).
- Experience with IC digital implementation flows and backend EDA tools: place & route, clock tree synthesis, IR drop analysis, backend timing, and power closure.
- Proven track record closing top-level chip projects and optimizing PPA under aggressive constraints.
- Experience with advanced nodes at 7nm and below.
- Proficiency in scripting languages (Tcl, Perl, Python).
- Strong customer-facing communication and problem-solving skills; ability to build technical relationships across RTL, DFT, CAD, and library teams.
- Demonstrated personal drive for continuous learning and expanding professional skills.
Education Requirements
Bachelor's degree in Computer Science/Engineering, Electrical Engineering, or a related field is required. Master’s degree in these fields is preferred.
About the Company
Company: Cadence Design Systems
Headquarters: San Jose, California, USA
Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.
