Back-End TD Reliability Lab Manager

Job Title

Back-End TD Reliability Lab Manager

Role Summary

Lead the Stress Test and Reliability (STaR) Back-End laboratory within the Foundry Lab Network at Intel's Chandler/ Phoenix site. Manage a laboratory team responsible for reliability qualification, stress testing, and Quick Turn Monitoring (QTM) for advanced packaging technologies.

Partner with Packaging Technology Development, Quality & Reliability, and Failure Analysis to develop lab capabilities, deliver timely data for qualification, and drive operational and quality excellence.

Experience Level

Senior-level engineering manager. The role requires demonstrated engineering leadership and at least 3+ years of engineering management experience in semiconductor packaging, reliability, test, or validation engineering.

Responsibilities

Manage laboratory operations, technical roadmap, and team performance to support reliability qualification and fast technology turnaround.

• Hire, coach, and develop a high-performing team of ~8–10 laboratory engineers.
• Define and execute laboratory capability and capacity roadmap to meet technology and customer needs.
• Oversee development and implementation of Reliability Quick Turn Monitoring (QTM) methodologies to accelerate time-to-data.
• Ensure timely responses to internal and external customer requirements and data requests.
• Lead laboratory quality management and readiness efforts toward ISO 17025 accreditation.
• Drive operational excellence, continuous improvement, and effective 8D/root-cause analysis processes.
• Coordinate cross-functional problem solving with Packaging Technology Development, Quality and Reliability, and Failure Analysis teams.
• Manage relationships with third-party stress labs and external partners as needed.

Requirements

Must-have technical skills and leadership experience; preferred items follow.

• Must-have: 3+ years of engineering management experience in semiconductor packaging, reliability engineering (product or process), test engineering, or validation engineering.
• Must-have: Demonstrated expertise in process qualification, reliability risk assessment, quality management systems, and developing a quality culture.
• Must-have: 2+ years of hands-on experience with reliability stress and testing.
• Must-have: Strong communication, stakeholder management, and the ability to influence cross-functional teams.
• Must-have: Ability to manage multiple priorities in fast-paced, resource-constrained environments.
• Preferred: Knowledge of reliability statistics and life prediction, including accelerated life testing (ALT) and sampling plans (AQL/SQL).
• Preferred: Experience with dynamics testing (shock and vibration) to JEDEC or similar standards and familiarity with JESD47 stress requirements.
• Preferred: Experience with advanced packaging assembly processes, defect/failure modes, and design-rule scaling.
• Preferred: Experience coordinating and auditing third-party stress laboratories.

Education Requirements

Minimum: Master’s degree in Electrical Engineering, Mechanical Engineering, Physics, Materials Science, or a related technical discipline.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.