Associate Staff/Staff Implementation Design Engineer

Job Title

Associate Staff/Staff Implementation Design Engineer

Role Summary

Lead implementation design engineer responsible for back-end (BE) implementation of high-performance SoCs and ASICs. Primary focus on synthesis, static timing analysis (STA), timing sign-off, low-power checks, and PPA optimization across process corners and operating modes.

Work within the Silicon Engineering team and collaborate with RTL, DFT, PnR, verification, and packaging teams to drive timing closure and physical design methodology improvements.

Experience Level

Senior — 9–10 years of ASIC physical design experience (as stated).

Responsibilities

Accountable for end-to-end BE implementation and timing sign-off; typical responsibilities include:

• Develop, manage and validate timing constraints for RTL-to-GDSII flow.
• Own STA execution for block and top-level designs and interpret timing reports.
• Generate CTS specs with PnR engineers and implement timing ECOs to fix critical paths.
• Run logic equivalence checks and low-power/UPF validation.
• Perform timing checks for CDC, false paths, and multicycle paths.
• Optimize PPA (power, performance, area) and manage synthesis strategies and sign-off criteria (timing, IR drop, EM, DRC/LVS).
• Drive EDA tool flow automation and methodology enhancements.
• Lead and mentor engineers through the full physical design cycle for complex SoCs and IP blocks.

Requirements

Must-have technical skills and experience:

• 9–10 years of ASIC physical design experience, including hands-on BE implementation.
• Proficiency with industry EDA tools such as Cadence (Genus, Innovus, Tempus, LEC, CLP) or Synopsys (ICC2, Fusion Compiler, PrimeTime).
• Strong background in synthesis, constraints, timing analysis, and timing-fix methodologies.
• Knowledge of low-power design techniques (UPF/CPF, power gating, DVFS) and low-power checks.
• Solid understanding of architecture-to-GDSII flows and sign-off requirements.
• Excellent problem-solving and communication skills.

Nice-to-have:

• Chip-level integration and hierarchical design methodology experience.
• Familiarity with DFT, floorplanning, place & route, and physical verification/IR analysis.
• Experience with multi-clock, multi-voltage, and multi-domain designs.
• Experience leading small teams (4–10 engineers).
• Automation skills (Perl, Tcl, Python).

Education Requirements

Bachelor’s or Master’s degree in Electrical/Electronic Engineering (ECE, EEE), VLSI, or a related technical field.

About the Company

Company: Silicon Labs

Headquarters: Austin, Texas, USA

Silicon Labs is a leading innovator in low-power wireless connectivity, creating embedded technology that connects devices to improve lives. With a focus on advanced edge connectivity applications, the company provides device makers with cutting-edge solutions and support. Headquartered in Austin, Texas, Silicon Labs operates in over 16 countries, serving markets such as smart home, industrial IoT, and smart cities.