Associate Engineer, Design Verification Engineering

Job Title

Associate Engineer, Design Verification Engineering

Role Summary

Entry-level individual contributor on the Sustainable Automation (SAU) team responsible for simulation-based verification of digital RTL blocks and subsystems to ensure functional correctness before silicon tape-out.

The role works closely with digital design engineers and cross-functional teams to develop and execute verification tests, analyze results, and support debugging and coverage closure.

Experience Level

Entry-level (Graduate). Suitable for new graduates or engineers with foundational verification experience; typically 0–2 years of relevant experience.

Responsibilities

Primary responsibilities include implementing and executing digital verification tasks for assigned blocks and subsystems.

• Execute digital RTL verification using simulation-based methodologies.
• Develop, maintain, and run SystemVerilog-based testbenches within established frameworks.
• Implement directed and basic constrained-random tests to validate functionality.
• Analyze simulation results, identify functional issues, and support root-cause debug with design engineers.
• Collect and contribute to functional and code coverage; assist in closing coverage gaps.
• Support regression testing and ensure repeatable, reliable verification results.
• Review design specifications and participate in verification and design reviews.
• Document verification status, test results, and identified issues clearly and accurately.
• Follow company verification methodologies, coding standards, and development processes.
• Continuously develop technical skills through mentoring, training, and project work.
• Travel as required (approximately 10%).

Requirements

Must-have technical skills and attributes for this role.

• Foundational understanding of digital logic and RTL design principles.
• Familiarity with SystemVerilog and/or Verilog.
• Basic knowledge of simulation-based functional verification concepts.
• Exposure to Linux/UNIX development environments.
• Strong analytical, debugging, and problem-solving skills.
• Effective written and verbal communication and the ability to work in a team.

Nice-to-have:

• Coursework, internship, or project experience in digital ASIC or SoC verification.
• Awareness of UVM concepts and introductory experience with SystemVerilog Assertions (SVA).
• Familiarity with functional and code coverage methodologies.
• Experience with scripting languages such as Python or Perl.
• Exposure to version control tools (Git, Perforce) and regression workflows.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical discipline is specified as the minimum qualification.

About the Company

Company: Analog Devices

Headquarters: Norwood, Massachusetts, USA

Analog Devices is a leading global semiconductor company that bridges the physical and digital worlds, enabling breakthroughs at the Intelligent Edge. With a focus on innovation, ADI develops solutions that drive advancements in digitized factories, mobility, and digital healthcare. The company employs around 24,000 people globally and reported revenues exceeding $9 billion in FY24, creating technologies that transform lives across various sectors.