ASIC / VLSI Engineers — RTL / STA / PD / DV (Senior)

Job Title

ASIC / VLSI Engineers — RTL / STA / PD / DV (Senior)

Role Summary

Senior, onsite ASIC/VLSI engineers to work on SoC/full-chip development for networking and AI programs within a semiconductor design services organization. Roles support long-term engagements with tier‑1 clients on advanced silicon projects.

Open positions: RTL Engineer (Networking), STA Engineer, Physical Design Engineer, Design Verification Engineer.

Experience Level

Senior level — 8+ years of pre-silicon ASIC/VLSI experience required.

Responsibilities

The selected engineers will contribute to SoC/full-chip design through RTL, timing, physical design, or verification activities and collaborate across functions to achieve tapeout and productization.

• Develop and review RTL, microarchitecture, or verification environments depending on role.
• Perform SoC-level timing analysis and closure (for STA role) or physical design tasks such as floorplanning, CTS, routing (for PD role).
• Implement and execute full verification lifecycles using SystemVerilog/UVM (for DV role).
• Collaborate with cross-functional teams (RTL, DV, PD) to drive tapeout readiness and productization.
• Use scripting (Python, Tcl, Perl) to automate flows and analyses.
• Optimize designs for timing, congestion, power, and manufacturability at advanced nodes.

Requirements

Must-have qualifications and experience.

• 8+ years of pre-silicon ASIC/VLSI experience at SoC/full-chip level.
• Strong digital logic fundamentals and RTL-based design experience.
• Experience across the ASIC lifecycle from design through tapeout (productization).
• Scripting proficiency (Python, Tcl, Perl, or similar).
• Role-specific must-haves:
  • RTL Engineer: Ethernet (802.3), MAC/PCS, SerDes/PHY, high‑speed design (100G+ preferred), tapeout experience.
  • STA Engineer: SoC-level timing analysis & closure; tools like PrimeTime or Tempus.
  • Physical Design Engineer: floorplanning, CTS, routing, signoff; timing, congestion, power optimization.
  • Design Verification Engineer: SoC-level verification, SystemVerilog/UVM, full verification lifecycle.
• Pre-silicon experience only; post-silicon/firmware-only backgrounds are not acceptable.

Nice-to-have: experience with complex SoC tapeouts and advanced process nodes (28nm and below).

Education Requirements

Not specified.

About the Company

Company: Etech Hi

Staffing and recruiting firm that connects engineering and semiconductor design talent with clients, supporting long-term engagements in networking, AI, and advanced silicon programs.