ASIC / VLSI Engineer (RTL / STA / PD / DV)

Job Title

ASIC / VLSI Engineer (RTL / STA / PD / DV)

Role Summary

Permanent, full-time onsite engineering roles in Milpitas supporting SoC/full-chip design for semiconductor and AI/networking programs within a design services organization working with tier-1 clients.

Positions cover RTL, Static Timing Analysis (STA), Physical Design (PD), and Design Verification (DV) and focus on pre-silicon development through tapeout and productization.

Experience Level

Senior — typically 8+ years of pre-silicon ASIC/VLSI experience.

Responsibilities

Work on SoC/full-chip pre-silicon activities across design, timing, physical implementation, and verification to support tapeout and productization.

• Implement and review RTL and microarchitecture for SoC-level blocks (RTL role).
• Perform SoC-level static timing analysis and timing closure using PrimeTime/Tempus or equivalent (STA role).
• Perform floorplanning, CTS, routing, congestion and power optimization, and signoff activities (PD role).
• Develop and execute SoC-level verification plans, testbenches, and UVM/SystemVerilog environments (DV role).
• Develop scripts and automation for flows (Python, Tcl, Perl).
• Collaborate with cross-functional teams (RTL, DV, PD) and participate in design reviews and tapeout readiness.

Requirements

Must-have skills and experience for all roles, followed by role-specific expectations and preferred qualifications.

• 8+ years of pre-silicon ASIC/VLSI experience.
• SoC / full-chip experience (not IP-only).
• Strong background in RTL-based design environments and digital logic fundamentals.
• Practical knowledge of the ASIC lifecycle from design through tapeout and productization.
• Scripting and automation experience (Python, Tcl, Perl, or similar).
• Pre-silicon focus only; no post-silicon/firmware-only backgrounds.
• Role-specific:
  • RTL Engineer: RTL design and microarchitecture; Ethernet (802.3), MAC/PCS, SerDes/PHY; high-speed design (100G+ preferred); tapeout experience.
  • STA Engineer: SoC-level timing analysis and closure; experience with PrimeTime, Tempus, or similar tools.
  • Physical Design Engineer: Floorplanning, CTS, routing, signoff; timing, congestion, and power optimization.
  • Design Verification Engineer: SoC-level verification; SystemVerilog and UVM; full verification lifecycle.
• Nice-to-have: Experience with complex SoC tapeouts, cross-functional collaboration, and advanced process nodes (28nm and below).

Education Requirements

Not specified.

About the Company

Company: Etech Hi

Staffing and recruiting firm that connects engineering and semiconductor design talent with clients, supporting long-term engagements in networking, AI, and advanced silicon programs.