ASIC Verification- Staff Engineer
The ASIC Verification- Staff Engineer will specify, architect, and implement advanced verification environments for DesignWare IP cores using System Verilog. The primary focus is to deliver high-quality, robust IP solutions for commercial, enterprise, and automotive applications through effective collaboration with designers and verification teams.
Mid-level (5+ years with BSEE or 3+ years with MSEE in ASIC or IP verification).
The responsibilities include:
Must-have skills and experience:
Not specified.
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
