ASIC Verification Lead

Job Title

ASIC Verification Lead

Role Summary

Lead verification strategy and execution for complex ASICs used in high-end and exascale servers. Drive UVM-based methodologies, develop verification environments and coverage models, and collaborate with architecture and design teams to ensure functional correctness and performance.

Location: Madrid or Barcelona, or remote within Spain.

Experience Level

Senior / Lead. No specific years of experience were stated in the posting.

Responsibilities

The role focuses on planning, implementing, and validating ASIC verification solutions and mentoring team members.

• Define verification strategy, methodologies, and required simulation environments.
• Develop, maintain, and publish verification specifications and detailed test plans.
• Design and implement UVM/SystemVerilog (and C++ where applicable) verification environments and coverage models.
• Run simulations, debug failures, analyze coverage results, and iterate tests to meet coverage targets.
• Recommend tools, flows, and methodology improvements to increase productivity.
• Mentor junior engineers and promote maintainable, reusable verification code and practices.
• Work closely with architecture and logical design teams to align verification with design intent.

Requirements

Key technical and practical qualifications. Education items from the original posting are summarized separately under Education Requirements.

• Must-have: Proven experience in functional verification of complex ASICs or SoCs; mastery of UVM or an equivalent verification methodology; strong SystemVerilog verification skills; experience with constrained-random, coverage-driven verification; ability to develop coverage models and verification environments; strong debugging and coverage-analysis skills; experience defining verification strategies and simulation environments; experience mentoring engineers.
• Nice-to-have: Experience with network controllers, routers, cache-coherence controllers, or other server-targeted IPs; experience using C++ in verification environments; prior work on high-performance or exascale server platforms; experience recommending and integrating EDA tools and flows.

Education Requirements

Bachelor's degree (BE / BTech) or Master's degree (ME / MTech) as stated in the posting.

About the Company

Company: World Grid