ASIC Verification Engineer, Staff
SynopsysJob Title
ASIC Verification Engineer, Staff
Role Summary
Lead verification activities for interface IP and subsystem integration used in advanced SoCs. Work with verification engineers, RTL designers, and architects to define verification strategy, deliver robust UVM/SystemVerilog testbenches, and ensure functional correctness and verification signoff.
Experience Level
Senior - typically 8+ years of experience in ASIC/FPGA verification with experience leading technical verification efforts.
Responsibilities
Primary responsibilities focused on technical leadership, verification architecture, and delivering high-quality verification results.
- Technically lead verification for critical areas and mentor verification engineers.
- Define, implement, and track comprehensive verification test plans and strategies.
- Specify, build, enhance, and maintain top-level UVM SystemVerilog testbenches integrating RTL and behavioral models.
- Develop, code, and debug test cases, checkers, and assertions in SystemVerilog/UVM.
- Extract, review, and drive closure of functional and code coverage metrics.
- Manage regression suites and contribute to verification automation and continuous improvement.
- Debug simulation failures, perform root-cause analysis, and coordinate fixes with RTL designers.
- Collaborate with architects and cross-functional teams to achieve verification signoff.
Requirements
Must-have technical skills and experience for this role.
- Proven track record of technically leading verification teams and managing stakeholders.
- Strong expertise in SystemVerilog and UVM; experience building and maintaining top-level testbenches.
- Experience writing complex checkers, assertions, and verification tests; strong debugging skills.
- Proficiency in extracting and analyzing functional and code coverage and driving metric closure.
- Ownership of end-to-end verification deliverables: planning, execution, metrics closure, and signoff.
- Familiarity with regression management and verification automation practices.
- Experience with interface protocols and IP verification processes; knowledge of DDR, HBM, PCIe, UCIe, Ethernet, or UALink is highly desirable.
Education Requirements
Bachelor's or Master's degree in Electronics/Electrical Engineering or a related technical field. The posting specifies 8+ years of ASIC/FPGA verification experience in addition to the degree requirement.
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
